From patchwork Tue Jan 28 17:02:45 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoph Fritz X-Patchwork-Id: 3547321 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 016A9C02DC for ; Tue, 28 Jan 2014 17:03:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1298F200F2 for ; Tue, 28 Jan 2014 17:03:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CFD1220160 for ; Tue, 28 Jan 2014 17:03:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755062AbaA1RC4 (ORCPT ); Tue, 28 Jan 2014 12:02:56 -0500 Received: from mail-lb0-f175.google.com ([209.85.217.175]:46548 "EHLO mail-lb0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754685AbaA1RCy (ORCPT ); Tue, 28 Jan 2014 12:02:54 -0500 Received: by mail-lb0-f175.google.com with SMTP id p9so588490lbv.34 for ; Tue, 28 Jan 2014 09:02:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20120113; h=subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version; bh=uZkces1g38RVNg5dGtK8fuJf7l2ATmnnaK5G0ZotRBM=; b=sTVjyW6NDevX3mHZ3CtVyt6DLRVl2zNsouTL+UNz4d/j25m+UF6efv9VH6aFa52PIq R/dGL85oyYb5LiI42AgCqMRHrCJzeqMU5JQDOwtdk6Hci7CmaC0cUouSClPIBy93IC+R JIJuCZFqCrAhwxX8A2XQhMC6PLMqp1lMVnXaTWrJhgo99m7lxGPARA7nUrZZV9bRN5Qs 60xIyzURXCxbkL97hPXt4nmOcxnSoqcMaj6WxAasQ+RibmgpEiKEks3ArsYwWuSf+ahg 4ezLM2uBERyIgn7U/qUrqFUE+Shu+JXxZQRWU7/XXeuTYwVUNs6RFCs4kztBcfPamsCl 705Q== X-Received: by 10.112.151.42 with SMTP id un10mr1570931lbb.7.1390928571006; Tue, 28 Jan 2014 09:02:51 -0800 (PST) Received: from [46.246.37.140] (anon-37-140.vpn.ipredator.se. [46.246.37.140]) by mx.google.com with ESMTPSA id ri4sm17659202lbb.6.2014.01.28.09.02.46 for (version=SSLv3 cipher=RC4-SHA bits=128/128); Tue, 28 Jan 2014 09:02:48 -0800 (PST) Subject: Re: [BISECTED] OMAP: DSS: clk rate mismatch From: Christoph Fritz To: Tero Kristo Cc: Tomi Valkeinen , Ivaylo Dimitrov , "linux-omap@vger.kernel.org" , linux-kernel@vger.kernel.org, pali.rohar@gmail.com, pavel@ucw.cz, Nishanth Menon In-Reply-To: <52E7B361.2030601@ti.com> References: <52E697C0.6000202@gmail.com> <1390848104.4936.62.camel@mars> <52E772A3.4090401@ti.com> <1390901735.2963.8.camel@lovely> <52E77D03.8090001@ti.com> <52E7B361.2030601@ti.com> Date: Tue, 28 Jan 2014 18:02:45 +0100 Message-ID: <1390928565.4904.88.camel@mars> Mime-Version: 1.0 X-Mailer: Evolution 2.30.3 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, T_TVD_MIME_EPI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Tue, 2014-01-28 at 15:40 +0200, Tero Kristo wrote: > On 01/28/2014 11:48 AM, Tomi Valkeinen wrote: > > On 2014-01-28 11:35, Christoph Fritz wrote: > >> On Tue, 2014-01-28 at 11:04 +0200, Tomi Valkeinen wrote: > >>> On 2014-01-27 20:41, Christoph Fritz wrote: > >>>> On Mon, 2014-01-27 at 19:30 +0200, Ivaylo Dimitrov wrote: > >>>>> linux-next-20140124 DSS is broken on N900 - display stays black (there > >>>>> is some noise though). I booted the kernel with qemu and it gives the > >>>>> following warning: > >>>>> > >>>>> [ 0.623779] DSS: set fck to 172800000 > >>>>> [ 0.624237] ------------[ cut here ]------------ > >>>>> [ 0.624298] WARNING: CPU: 0 PID: 1 at > >>>>> drivers/video/omap2/dss/dss.c:497 dss_set_fck_rate+0x68/0x8c() > >>>>> [ 0.624359] clk rate mismatch: 288000000 != 172800000 > >>>> > >>>> Here are also clock regressions since next-20140122 regarding > >>>> dss_set_fck_rate() and sys_clkout2 occuring in my current patchset for a > >>>> dm37xx100 board. Please see here: > >>> > >>> I presume you get a similar warning on your board? What rates does it > >>> report? > >> > >> None, dss_set_fck_rate() just fails so omapdss_dss exits with error -22. > > > > Ok, then it's something else. That means clk_set_rate() fails. > > > > If you can do some tests, you could print the rate that the > > dss_set_fck_rate() is given, to see that it's something reasonable, and > > also do a clk_get_rate(dss.dss_clk) to see that the clock itself is ok > > and there's some valid rate there. > > > >> To quote the cover-letter[1] of my board-support patch series here: > >> > >> Due to a regression since next-20140122 the following errors are present: > >> > >> - pin sys_clkout2, which gets configured to 24 Mhz by the fourth patch > >> in this set, erroneously outputs only 12 Mhz. > >> Just out of curiosity, configuring it to 48 Mhz puts out desired 24 Mhz. > >> > >> - omap_dss, which gets configured by the third patch in this set, fails > >> to do 'dss_set_fck_rate(fck);' in > >> drivers/video/omap2/dss/dss.c:dss_setup_default_clock() which leads to: > >> > >> | omapdss_dss: probe of omapdss_dss failed with error -22 > >> | omapdss CORE error: Failed to initialize DSS platform driver > >> | panel-dpi panel-dpi.0: failed to find video source 'dpi.0 > >> > >> Both regressions seem to have something to do with the clock framework. > >> Could this be related to the DT clock conversion patches? > > > > No idea... > > Yea its definitely possible, as the clock DT conversion touches pretty > much everything. Have you tried whether this works properly with legacy > boot? Personally I don't have access to any omap3 devices that would > have display and have no possibility to check this out myself. Anyway, > my initial guess is that some clock divider setup might be wrong with > omap3, or we are missing some ti,set-rate-parent flag for some clock > node which prevents escalating clk_set_rate properly. However, it should > be easy to debug this by looking at the clock node in question, and its > parent nodes to see if there are any problems. Currently I only analyzed sys_clkout2 (see attachments for full clk_summary files): clk_summary__next-20140115__works_as_expected: dpll4_m2_ck 1 1 96000000 dpll4_m2x2_ck 1 1 96000000 omap_192m_alwon_fck 1 1 96000000 omap_96m_alwon_fck 1 2 96000000 per_96m_fck 0 6 96000000 mcbsp4_fck 0 1 96000000 mcbsp3_fck 0 2 96000000 mcbsp2_fck 0 2 96000000 cm_96m_fck 2 3 96000000 clkout2_src_ck 1 1 96000000 sys_clkout2 1 1 24000000 For real, on pin sys_clkout2 are correctly 24 Mhz measured. clk_summary__next-20140124__sysclkout2_dss_fails: dpll4_m2_ck 1 1 96000000 dpll4_m2x2_mul_ck 1 1 192000000 dpll4_m2x2_ck 1 1 192000000 omap_192m_alwon_fck 0 0 192000000 omap_96m_alwon_fck 1 2 192000000 per_96m_fck 0 6 192000000 mcbsp4_fck 0 1 192000000 mcbsp3_fck 0 2 192000000 mcbsp2_fck 0 2 192000000 cm_96m_fck 2 3 192000000 clkout2_src_ck 1 1 192000000 sys_clkout2 1 1 24000000 For real, on pin sys_clkout2 are only ~12 Mhz measured. So I added this patch: From c1f8a2aa60cb8973f7eeeb517fb067b1fce66c1f Mon Sep 17 00:00:00 2001 From: Christoph Fritz Date: Tue, 28 Jan 2014 17:35:10 +0100 Subject: [PATCH] ARM: dts: fix omap3 clock multiplier for dpll4_m2x2_ck Before DT clock conversion, there was no multiplier for dpll4_m2x2_ck. So to be compatible again, set dpll4_m2x2_mul_ck multiplier back to 1. --- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index cb04d4b..b594050 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -212,7 +212,7 @@ #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&dpll4_m2_ck>; - clock-mult = <2>; + clock-mult = <1>; clock-div = <1>; };