From patchwork Wed Feb 5 13:28:30 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: pekon gupta X-Patchwork-Id: 3586041 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A85C1C02DC for ; Wed, 5 Feb 2014 13:28:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 149E720115 for ; Wed, 5 Feb 2014 13:28:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 34FF520181 for ; Wed, 5 Feb 2014 13:28:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751289AbaBEN2m (ORCPT ); Wed, 5 Feb 2014 08:28:42 -0500 Received: from arroyo.ext.ti.com ([192.94.94.40]:56504 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750985AbaBEN2m (ORCPT ); Wed, 5 Feb 2014 08:28:42 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s15DSeQe024958; Wed, 5 Feb 2014 07:28:40 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s15DSeGK010173; Wed, 5 Feb 2014 07:28:40 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Wed, 5 Feb 2014 07:28:39 -0600 Received: from psplinux063.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s15DSa5c010180; Wed, 5 Feb 2014 07:28:39 -0600 From: Pekon Gupta To: Tony Lindgren , CC: linux-omap , Pekon Gupta Subject: [PATCH v1 1/5] ARM: OMAP2+: gpmc: update gpmc_hwecc_bch_capable() for new platforms and ECC schemes Date: Wed, 5 Feb 2014 18:58:30 +0530 Message-ID: <1391606914-9947-2-git-send-email-pekon@ti.com> X-Mailer: git-send-email 1.8.5.1.163.gd7aced9 In-Reply-To: <1391606914-9947-1-git-send-email-pekon@ti.com> References: <1391606914-9947-1-git-send-email-pekon@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch - refactors gpmc_hwecc_bch_capable() - add checks for new platforms like dra7xx, am43xx - add checks for OMAP3 SoC, w.r.t. new ECC schemes spawned in following commit: commit ac65caf514ec3e55e8d3d510ee37f80dd97418fe ARM: OMAP2+: cleaned-up DT support of various ECC schemes Signed-off-by: Pekon Gupta --- arch/arm/mach-omap2/gpmc-nand.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index 174caec..4349e82 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -45,24 +45,31 @@ static struct platform_device gpmc_nand_device = { static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) { - /* support only OMAP3 class */ - if (!cpu_is_omap34xx() && !soc_is_am33xx()) { - pr_err("BCH ecc is not supported on this CPU\n"); + /* platforms which support all ECC schemes */ + if (soc_is_am33xx() || cpu_is_omap44xx() || + soc_is_omap54xx() || soc_is_dra7xx()) + return 1; + + /* OMAP3xxx do not have ELM engine, so cannot support ECC schemes + * which require H/W based ECC error detection */ + if ((cpu_is_omap34xx() || cpu_is_omap3630()) && + ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) || + (ecc_opt == OMAP_ECC_BCH8_CODE_HW))) return 0; - } /* * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1 * and AM33xx derivates. Other chips may be added if confirmed to work. */ - if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) && - (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) && - (!soc_is_am33xx())) { - pr_err("BCH 4-bit mode is not supported on this CPU\n"); + if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW) && + (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) return 0; - } - return 1; + /* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */ + if (ecc_opt == OMAP_ECC_HAM1_CODE_HW) + return 1; + else + return 0; } /* This function will go away once the device-tree convertion is complete */ @@ -133,8 +140,10 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); - if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) + if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) { + dev_err(dev, "Unsupported NAND ECC scheme selected\n"); return -EINVAL; + } err = platform_device_register(&gpmc_nand_device); if (err < 0) {