From patchwork Wed Feb 5 13:28:33 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: pekon gupta X-Patchwork-Id: 3586051 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2DD809F2E9 for ; Wed, 5 Feb 2014 13:28:51 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3DBC820181 for ; Wed, 5 Feb 2014 13:28:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2AC0020115 for ; Wed, 5 Feb 2014 13:28:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751362AbaBEN2s (ORCPT ); Wed, 5 Feb 2014 08:28:48 -0500 Received: from arroyo.ext.ti.com ([192.94.94.40]:56512 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750985AbaBEN2r (ORCPT ); Wed, 5 Feb 2014 08:28:47 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s15DSjdh025217; Wed, 5 Feb 2014 07:28:45 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s15DSjaC015591; Wed, 5 Feb 2014 07:28:45 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Wed, 5 Feb 2014 07:28:45 -0600 Received: from psplinux063.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s15DSa5f010180; Wed, 5 Feb 2014 07:28:44 -0600 From: Pekon Gupta To: Tony Lindgren , CC: linux-omap , Minal Shah , Pekon Gupta Subject: [PATCH v1 4/5] ARM: dts: dra7: add support for parallel NAND flash Date: Wed, 5 Feb 2014 18:58:33 +0530 Message-ID: <1391606914-9947-5-git-send-email-pekon@ti.com> X-Mailer: git-send-email 1.8.5.1.163.gd7aced9 In-Reply-To: <1391606914-9947-1-git-send-email-pekon@ti.com> References: <1391606914-9947-1-git-send-email-pekon@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Minal Shah DRA7xx platform has in-build GPMC and ELM h/w engines which can be used for accessing externel NAND flash device. This patch: - adds generic DT binding in dra7.dtsi for enabling GPMC and ELM h/w engines - adds DT binding for Micron NAND Flash (MT29F2G16AADWP) present on dra7-evm *Important* On DRA7 EVM, GPMC_WPN and NAND_BOOTn are controlled by DIP switch So following board settings are required for NAND device detection: SW5.9 (GPMC_WPN) = LOW SW5.1 (NAND_BOOTn) = HIGH Signed-off-by: Minal Shah Signed-off-by: Pekon Gupta --- arch/arm/boot/dts/dra7-evm.dts | 117 +++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/dra7.dtsi | 20 +++++++ 2 files changed, 137 insertions(+) diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 5babba0..81c5f7f 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -93,6 +93,37 @@ 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */ >; }; + + nand_flash_x16: nand_flash_x16 { + /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch + * So NAND flash requires following switch settings: + * SW5.9 (GPMC_WPN) = LOW + * SW5.1 (NAND_BOOTn) = HIGH */ + pinctrl-single,pins = < + 0x0 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad0 */ + 0x4 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad1 */ + 0x8 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad2 */ + 0xc 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad3 */ + 0x10 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad4 */ + 0x14 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad5 */ + 0x18 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad6 */ + 0x1c 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad7 */ + 0x20 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad8 */ + 0x24 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad9 */ + 0x28 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad10 */ + 0x2c 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad11 */ + 0x30 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad12 */ + 0x34 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad13 */ + 0x38 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad14 */ + 0x3c 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_ad15 */ + 0xD8 0x70000 /* (PIN_INPUT | MUX_MODE0) gpmc_wait0 */ + 0xCC 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_wen */ + 0xB4 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_csn0 */ + 0xC4 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_advn_ale */ + 0xC8 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_oen_ren */ + 0xD0 0x0 /* (PIN_OUTPUT | MUX_MODE0) gpmc_be0n_cle */ + >; + }; }; &i2c1 { @@ -273,3 +304,89 @@ &cpu0 { cpu0-supply = <&smps123_reg>; }; + +&elm { + status = "okay"; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nand_flash_x16>; + ranges = <0 0 0x08000000 0x10000000>; + nand@0,0 { + reg = <0 0 0>; + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + nand-bus-width = <16>; + gpmc,device-width = <2>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <40>; + gpmc,cs-wr-off-ns = <40>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <30>; + gpmc,adv-wr-off-ns = <30>; + gpmc,we-on-ns = <5>; + gpmc,we-off-ns = <25>; + gpmc,oe-on-ns = <2>; + gpmc,oe-off-ns = <20>; + gpmc,access-ns = <20>; + gpmc,wr-access-ns = <40>; + gpmc,rd-cycle-ns = <40>; + gpmc,wr-cycle-ns = <40>; + gpmc,wait-on-read = "true"; + gpmc,wait-on-write = "true"; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + /* MTD partition table */ + /* All SPL-* partitions are sized to minimal length + * which can be independently programmable. For + * NAND flash this is equal to size of erase-block */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "NAND.SPL"; + reg = <0x00000000 0x000020000>; + }; + partition@1 { + label = "NAND.SPL.backup1"; + reg = <0x00020000 0x00020000>; + }; + partition@2 { + label = "NAND.SPL.backup2"; + reg = <0x00040000 0x00020000>; + }; + partition@3 { + label = "NAND.SPL.backup3"; + reg = <0x00060000 0x00020000>; + }; + partition@4 { + label = "NAND.u-boot-spl-os"; + reg = <0x00080000 0x00040000>; + }; + partition@5 { + label = "NAND.u-boot"; + reg = <0x000C0000 0x00100000>; + }; + partition@6 { + label = "NAND.u-boot-env"; + reg = <0x001C0000 0x00020000>; + }; + partition@7 { + label = "NAND.u-boot-env"; + reg = <0x001E0000 0x00020000>; + }; + partition@8 { + label = "NAND.kernel"; + reg = <0x00200000 0x00800000>; + }; + partition@9 { + label = "NAND.file-system"; + reg = <0x00A00000 0x0F600000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 1fd75aa..5965bc3 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -621,6 +621,26 @@ dma-names = "tx0", "rx0"; status = "disabled"; }; + + elm: elm@48078000 { + compatible = "ti,am3352-elm"; + reg = <0x48078000 0x2000>; + interrupts = ; + ti,hwmods = "elm"; + status = "disabled"; + }; + + gpmc: gpmc@50000000 { + compatible = "ti,am3352-gpmc"; + ti,hwmods = "gpmc"; + reg = <0x50000000 0x2000>; + interrupts = ; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + status = "disabled"; + }; }; };