From patchwork Mon Feb 10 21:54:44 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Pinchart X-Patchwork-Id: 3623851 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E8C8EC02E3 for ; Mon, 10 Feb 2014 21:54:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2151A201E9 for ; Mon, 10 Feb 2014 21:54:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4BFB6201E7 for ; Mon, 10 Feb 2014 21:54:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753055AbaBJVyH (ORCPT ); Mon, 10 Feb 2014 16:54:07 -0500 Received: from perceval.ideasonboard.com ([95.142.166.194]:42214 "EHLO perceval.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752931AbaBJVxx (ORCPT ); Mon, 10 Feb 2014 16:53:53 -0500 Received: from avalon.ideasonboard.com (214.131-246-81.adsl-dyn.isp.belgacom.be [81.246.131.214]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 72712363D0; Mon, 10 Feb 2014 22:52:47 +0100 (CET) From: Laurent Pinchart To: linux-media@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org Subject: [PATCH 5/5] mt9p031: Add support for PLL bypass Date: Mon, 10 Feb 2014 22:54:44 +0100 Message-Id: <1392069284-18024-6-git-send-email-laurent.pinchart@ideasonboard.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1392069284-18024-1-git-send-email-laurent.pinchart@ideasonboard.com> References: <1392069284-18024-1-git-send-email-laurent.pinchart@ideasonboard.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When the input clock frequency is out of bounds for the PLL, bypass the PLL and just divide the input clock to achieve the requested output frequency. Signed-off-by: Laurent Pinchart --- drivers/media/i2c/mt9p031.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index 14a616e..5483ab2 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c @@ -78,6 +78,9 @@ #define MT9P031_PLL_CONFIG_1 0x11 #define MT9P031_PLL_CONFIG_2 0x12 #define MT9P031_PIXEL_CLOCK_CONTROL 0x0a +#define MT9P031_PIXEL_CLOCK_INVERT (1 << 15) +#define MT9P031_PIXEL_CLOCK_SHIFT(n) ((n) << 8) +#define MT9P031_PIXEL_CLOCK_DIVIDE(n) ((n) << 0) #define MT9P031_FRAME_RESTART 0x0b #define MT9P031_SHUTTER_DELAY 0x0c #define MT9P031_RST 0x0d @@ -130,6 +133,8 @@ struct mt9p031 { enum mt9p031_model model; struct aptina_pll pll; + unsigned int clk_div; + bool use_pll; int reset; struct v4l2_ctrl_handler ctrls; @@ -198,6 +203,11 @@ static int mt9p031_reset(struct mt9p031 *mt9p031) if (ret < 0) return ret; + ret = mt9p031_write(client, MT9P031_PIXEL_CLOCK_CONTROL, + MT9P031_PIXEL_CLOCK_DIVIDE(mt9p031->clk_div)); + if (ret < 0) + return ret; + return mt9p031_set_output_control(mt9p031, MT9P031_OUTPUT_CONTROL_CEN, 0); } @@ -232,8 +242,24 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) if (ret < 0) return ret; + /* If the external clock frequency is out of bounds for the PLL use the + * pixel clock divider only and disable the PLL. + */ + if (pdata->ext_freq > limits.ext_clock_max) { + unsigned int div; + + div = DIV_ROUND_UP(pdata->ext_freq, pdata->target_freq); + div = roundup_pow_of_two(div) / 2; + + mt9p031->clk_div = max_t(unsigned int, div, 64); + mt9p031->use_pll = false; + + return 0; + } + mt9p031->pll.ext_clock = pdata->ext_freq; mt9p031->pll.pix_clock = pdata->target_freq; + mt9p031->use_pll = true; return aptina_pll_calculate(&client->dev, &limits, &mt9p031->pll); } @@ -243,6 +269,9 @@ static int mt9p031_pll_enable(struct mt9p031 *mt9p031) struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); int ret; + if (!mt9p031->use_pll) + return 0; + ret = mt9p031_write(client, MT9P031_PLL_CONTROL, MT9P031_PLL_CONTROL_PWRON); if (ret < 0) @@ -268,6 +297,9 @@ static inline int mt9p031_pll_disable(struct mt9p031 *mt9p031) { struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); + if (!mt9p031->use_pll) + return 0; + return mt9p031_write(client, MT9P031_PLL_CONTROL, MT9P031_PLL_CONTROL_PWROFF); }