From patchwork Wed Apr 16 13:14:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: archit taneja X-Patchwork-Id: 4001151 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2BC329F2BA for ; Wed, 16 Apr 2014 13:15:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6B56620279 for ; Wed, 16 Apr 2014 13:15:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5A5AF20272 for ; Wed, 16 Apr 2014 13:15:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756278AbaDPNPy (ORCPT ); Wed, 16 Apr 2014 09:15:54 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:41814 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756260AbaDPNPx (ORCPT ); Wed, 16 Apr 2014 09:15:53 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id s3GDFVbO029694; Wed, 16 Apr 2014 08:15:31 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3GDFVfY017458; Wed, 16 Apr 2014 08:15:31 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Wed, 16 Apr 2014 08:15:30 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3GDFVhH004653; Wed, 16 Apr 2014 08:15:31 -0500 Received: from localhost (a0393947pc.apr.dhcp.ti.com [172.24.145.166]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id s3GDFTt16332; Wed, 16 Apr 2014 08:15:29 -0500 (CDT) From: Archit Taneja To: CC: , , Archit Taneja Subject: [RFC 3/4] ARM: dts: Add dss_deshdcp clock node under dra7-ctrl-core Date: Wed, 16 Apr 2014 18:44:22 +0530 Message-ID: <1397654063-8055-3-git-send-email-archit@ti.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1397654063-8055-1-git-send-email-archit@ti.com> References: <1397654063-8055-1-git-send-email-archit@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The DESHDCP clock is required only by the DES-HDCP block within HDMI in DSS. However, if the clock isn't set before DSS clock domian is enabled, the clock domain never comes out of idle state. The DESHDCP clock is enabled/disabled at the DSS boundary by the bit DSS_DESHDCP_CLKEN in CTRL_CORE_CONTROL_IO_2. Add dss_deshdcp gate-clock node under dra7-ctrl-core. There are separate bit fields for enabling and disabling the clock. We just map the enable bit since this clock doesn't cause any impact if left enabled. Signed-off-by: Archit Taneja --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index e96da9a..78d309c 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -2007,6 +2007,16 @@ }; }; +&ctrl_core_clocks { + dss_deshdcp_clk: dss_deshdcp_clk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&l3_iclk_div>; + ti,bit-shift = <0>; + reg = <0x0558>; + }; +}; + &cm_core_clockdomains { coreaon_clkdm: coreaon_clkdm { compatible = "ti,clockdomain";