From patchwork Wed Apr 16 13:14:23 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: archit taneja X-Patchwork-Id: 4001161 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8E916BFF02 for ; Wed, 16 Apr 2014 13:15:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AB98F20272 for ; Wed, 16 Apr 2014 13:15:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B9E4E2027D for ; Wed, 16 Apr 2014 13:15:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030180AbaDPNP4 (ORCPT ); Wed, 16 Apr 2014 09:15:56 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:54835 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756273AbaDPNPz (ORCPT ); Wed, 16 Apr 2014 09:15:55 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s3GDFYZG014520; Wed, 16 Apr 2014 08:15:34 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3GDFYG6017506; Wed, 16 Apr 2014 08:15:34 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.174.1; Wed, 16 Apr 2014 08:15:33 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3GDFXZK004682; Wed, 16 Apr 2014 08:15:33 -0500 Received: from localhost (a0393947pc.apr.dhcp.ti.com [172.24.145.166]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id s3GDFWt16337; Wed, 16 Apr 2014 08:15:32 -0500 (CDT) From: Archit Taneja To: CC: , , Archit Taneja Subject: [RFC 4/4] CLK: TI: Enable dss_deshdcp clock in dra7xx_clk_init Date: Wed, 16 Apr 2014 18:44:23 +0530 Message-ID: <1397654063-8055-4-git-send-email-archit@ti.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1397654063-8055-1-git-send-email-archit@ti.com> References: <1397654063-8055-1-git-send-email-archit@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The DESHDCP clock is required only by the DES-HDCP block within HDMI in DSS. However, if the clock isn't set before DSS clock domian is enabled, the clock domain never comes out of idle state. This is because the DSS IP is designed in such a way that if DES-HDCP block can't transition from idle state, the entire DSS clock domain also cannot transition from idle to enabled. DES-HDCP block needs the DESHDCP clock enabled to transition from idle successfully. We enable the deshdcp clock in dra7xx_clk_init() which happens before omap hwmods are setup. This clock is effectively a gate clock with the parent as DSS_L3_GICLK. The parent is an automatically controlled clock by DSS clock domain and hence doesn't have a clock node associated to it. Since DSS_L3_GICLK is derived from the OCP clock, we set the dss_deshdcp_clk's parent as l3_iclk_div. Leaving this bit enabled doesn't prevent DSS or the system to suspend, and only a very few flops get this clock all the time. So there is negligible impact. Signed-off-by: Archit Taneja --- drivers/clk/ti/clk-7xx.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index f7e4073..3f73a02 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c @@ -179,6 +179,7 @@ static struct ti_dt_clk dra7xx_clks[] = { DT_CLK(NULL, "dss_hdmi_clk", "dss_hdmi_clk"), DT_CLK(NULL, "dss_video1_clk", "dss_video1_clk"), DT_CLK(NULL, "dss_video2_clk", "dss_video2_clk"), + DT_CLK(NULL, "dss_deshdcp_clk", "dss_deshdcp_clk"), DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), @@ -306,7 +307,7 @@ static struct ti_dt_clk dra7xx_clks[] = { int __init dra7xx_dt_clk_init(void) { int rc; - struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck; + struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck, *dss_deshdcp_ck; ti_dt_clocks_register(dra7xx_clks); @@ -327,5 +328,10 @@ int __init dra7xx_dt_clk_init(void) if (rc) pr_err("%s: failed to configure GMAC DPLL!\n", __func__); + dss_deshdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk"); + rc = clk_prepare_enable(dss_deshdcp_ck); + if (rc) + pr_err("%s: failed to enable DESHDCP clock\n", __func__); + return rc; }