From patchwork Thu Apr 17 20:49:33 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 4011171 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9DB079F319 for ; Thu, 17 Apr 2014 20:57:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C0090202B4 for ; Thu, 17 Apr 2014 20:57:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D76E5202A1 for ; Thu, 17 Apr 2014 20:57:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752527AbaDQUvn (ORCPT ); Thu, 17 Apr 2014 16:51:43 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:40729 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751686AbaDQUu3 (ORCPT ); Thu, 17 Apr 2014 16:50:29 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id s3HKnboD019885; Thu, 17 Apr 2014 15:49:38 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3HKnbDe029831; Thu, 17 Apr 2014 15:49:37 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Thu, 17 Apr 2014 15:49:37 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3HKnb1R021832; Thu, 17 Apr 2014 15:49:37 -0500 From: Nishanth Menon To: Tony Lindgren , Santosh Shilimkar , Sricharan R CC: Sekhar Nori , Rajendra Nayak , Nishanth Menon , Peter Ujfalusi , , , , Subject: [PATCH V2 17/19] bus: omap_l3_noc: introduce concept of submodule Date: Thu, 17 Apr 2014 15:49:33 -0500 Message-ID: <1397767775-10965-18-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1397767775-10965-1-git-send-email-nm@ti.com> References: <1397492726-17203-1-git-send-email-nm@ti.com> <1397767775-10965-1-git-send-email-nm@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP While OMAP4 and OMAP5 had 3 separate clock domains, DRA7 has only 2 and the first one then is internally divided into 2 sub clock domains. To better represent this in the driver, we use the concept of submodule. The address defintions in the devicetree is as per the high level clock domain(module) base, the sub clockdomain/subdomain which shares the same register space of a clockdomain is marked in the SoC data as L3_BASE_IS_SUBMODULE. L3_BASE_IS_SUBMODULE is used as an indication that it's base address is the same as the parent module and offsets are considered from the same base address as they are usually intermingled. Other than the base address, the submodule is same as a module as it is functionally so. Signed-off-by: Nishanth Menon --- V2: reordering only. no functional change. V1: https://patchwork.kernel.org/patch/3984351/ drivers/bus/omap_l3_noc.c | 17 ++++++++++++----- drivers/bus/omap_l3_noc.h | 6 +++++- 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/bus/omap_l3_noc.c b/drivers/bus/omap_l3_noc.c index 9e68d6b..cf923f1 100644 --- a/drivers/bus/omap_l3_noc.c +++ b/drivers/bus/omap_l3_noc.c @@ -233,7 +233,7 @@ static int omap_l3_probe(struct platform_device *pdev) { const struct of_device_id *of_id; static struct omap_l3 *l3; - int ret, i; + int ret, i, res_idx; of_id = of_match_device(l3_noc_match, &pdev->dev); if (!of_id) { @@ -250,15 +250,22 @@ static int omap_l3_probe(struct platform_device *pdev) platform_set_drvdata(pdev, l3); /* Get mem resources */ - for (i = 0; i < l3->num_modules; i++) { - struct resource *res = platform_get_resource(pdev, - IORESOURCE_MEM, i); - + for (i = 0, res_idx = 0; i < l3->num_modules; i++) { + struct resource *res; + + if (l3->l3_base[i] == L3_BASE_IS_SUBMODULE) { + /* First entry cannot be submodule */ + BUG_ON(i == 0); + l3->l3_base[i] = l3->l3_base[i - 1]; + continue; + } + res = platform_get_resource(pdev, IORESOURCE_MEM, res_idx); l3->l3_base[i] = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(l3->l3_base[i])) { dev_err(l3->dev, "ioremap %d failed\n", i); return PTR_ERR(l3->l3_base[i]); } + res_idx++; } /* diff --git a/drivers/bus/omap_l3_noc.h b/drivers/bus/omap_l3_noc.h index 49258bb..9df9f25 100644 --- a/drivers/bus/omap_l3_noc.h +++ b/drivers/bus/omap_l3_noc.h @@ -41,6 +41,8 @@ #define L3_TARGET_NOT_SUPPORTED NULL +#define L3_BASE_IS_SUBMODULE ((void __iomem *)(1 << 0)) + static const char * const l3_transaction_type[] = { /* 0 0 0 */ "Idle", /* 0 0 1 */ "Write", @@ -92,7 +94,9 @@ struct l3_flagmux_data { /** * struct omap_l3 - Description of data relevant for L3 bus. * @dev: device representing the bus (populated runtime) - * @l3_base: base addresses of modules (populated runtime) + * @l3_base: base addresses of modules (populated runtime if 0) + * if set to L3_BASE_IS_SUBMODULE, then uses previous + * module index as the base address * @l3_flag_mux: array containing flag mux data per module * offset from corresponding module base indexed per * module.