From patchwork Fri Apr 25 08:55:25 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Poddar, Sourav" X-Patchwork-Id: 4058121 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3E20D9F319 for ; Fri, 25 Apr 2014 08:56:03 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 516432039E for ; Fri, 25 Apr 2014 08:56:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7284220398 for ; Fri, 25 Apr 2014 08:56:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751305AbaDYI4A (ORCPT ); Fri, 25 Apr 2014 04:56:00 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:39486 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750719AbaDYIz5 (ORCPT ); Fri, 25 Apr 2014 04:55:57 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id s3P8tVU8031659; Fri, 25 Apr 2014 03:55:31 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3P8tVDl021054; Fri, 25 Apr 2014 03:55:31 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Fri, 25 Apr 2014 03:55:31 -0500 Received: from ula0131647.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3P8tRDh004650; Fri, 25 Apr 2014 03:55:28 -0500 From: Sourav Poddar To: , , , , , , CC: Sourav Poddar Subject: [PATCH] arm: dts: am33xx-clock: Fix ehrpwm tbclk data. Date: Fri, 25 Apr 2014 14:25:25 +0530 Message-ID: <1398416125-7139-1-git-send-email-sourav.poddar@ti.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP tbclk does not need to be a composite clock, we can simply use gate clock for this purpose. Signed-off-by: Sourav Poddar --- arch/arm/boot/dts/am33xx-clocks.dtsi | 42 ++++++++++------------------------ 1 file changed, 12 insertions(+), 30 deletions(-) diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi index 9ccfe50..a45d27f 100644 --- a/arch/arm/boot/dts/am33xx-clocks.dtsi +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi @@ -96,46 +96,28 @@ clock-div = <1>; }; - ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk { + ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 { #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; + compatible = "gate-clock"; clocks = <&dpll_per_m2_ck>; - ti,bit-shift = <0>; - reg = <0x0664>; + bit-shift = <0>; + reg = <0x44e10664 0x4>; }; - ehrpwm0_tbclk: ehrpwm0_tbclk { + ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 { #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&ehrpwm0_gate_tbclk>; - }; - - ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk { - #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; + compatible = "gate-clock"; clocks = <&dpll_per_m2_ck>; - ti,bit-shift = <1>; - reg = <0x0664>; - }; - - ehrpwm1_tbclk: ehrpwm1_tbclk { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&ehrpwm1_gate_tbclk>; + bit-shift = <1>; + reg = <0x44e10664 0x4>; }; - ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk { + ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 { #clock-cells = <0>; - compatible = "ti,composite-no-wait-gate-clock"; + compatible = "gate-clock"; clocks = <&dpll_per_m2_ck>; - ti,bit-shift = <2>; - reg = <0x0664>; - }; - - ehrpwm2_tbclk: ehrpwm2_tbclk { - #clock-cells = <0>; - compatible = "ti,composite-clock"; - clocks = <&ehrpwm2_gate_tbclk>; + bit-shift = <2>; + reg = <0x44e10664 0x4>; }; }; &prcm_clocks {