From patchwork Fri Apr 25 23:02:39 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Fernandes X-Patchwork-Id: 4066961 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D6048BFF02 for ; Fri, 25 Apr 2014 23:07:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 164182021A for ; Fri, 25 Apr 2014 23:07:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2EEFD200CF for ; Fri, 25 Apr 2014 23:07:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752346AbaDYXDW (ORCPT ); Fri, 25 Apr 2014 19:03:22 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:48397 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750928AbaDYXDT (ORCPT ); Fri, 25 Apr 2014 19:03:19 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id s3PN2sSi007154; Fri, 25 Apr 2014 18:02:54 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3PN2s9w019230; Fri, 25 Apr 2014 18:02:54 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Fri, 25 Apr 2014 18:02:54 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3PN2spi016483; Fri, 25 Apr 2014 18:02:54 -0500 Received: from joel-laptop.am.dhcp.ti.com (joel-laptop.am.dhcp.ti.com [10.247.29.57]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id s3PN2rt28967; Fri, 25 Apr 2014 18:02:53 -0500 (CDT) From: Joel Fernandes To: Tony Lindgren , Benoit Cousson , Linux OMAP List , Linux ARM Kernel List , Linux Kernel Mailing List CC: Joel Fernandes Subject: [PATCH 01/10] ARM: OMAP: hwmod: Add SYSC offsets for AES IP Date: Fri, 25 Apr 2014 18:02:39 -0500 Message-ID: <1398466968-29506-2-git-send-email-joelf@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1398466968-29506-1-git-send-email-joelf@ti.com> References: <1398466968-29506-1-git-send-email-joelf@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The AES IP has the SIDLE offset by 2 and not 3, to allow SIDLE modes to work for AES, we add a new SYSC type to HWMOD code. Signed-off-by: Joel Fernandes --- arch/arm/mach-omap2/omap_hwmod.h | 11 +++++++++++ arch/arm/mach-omap2/omap_hwmod_common_data.c | 10 ++++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index 0f97d63..b2efcc8 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -41,6 +41,7 @@ struct omap_device; extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1; extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2; extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3; +extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type4; /* * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant @@ -81,6 +82,16 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3; #define SYSC_TYPE3_MIDLEMODE_SHIFT 2 #define SYSC_TYPE3_MIDLEMODE_MASK (0x3 << SYSC_TYPE3_MIDLEMODE_SHIFT) +/* + * OCP SYSCONFIG bit shifts/masks TYPE4. + */ +#define SYSC_TYPE4_SIDLEMODE_SHIFT 2 +#define SYSC_TYPE4_SIDLEMODE_MASK (0x3 << SYSC_TYPE4_SIDLEMODE_SHIFT) +#define SYSC_TYPE4_SOFTRESET_SHIFT 1 +#define SYSC_TYPE4_SOFTRESET_MASK (1 << SYSC_TYPE4_SOFTRESET_SHIFT) +#define SYSC_TYPE4_AUTOIDLE_SHIFT 0 +#define SYSC_TYPE4_AUTOIDLE_MASK (1 << SYSC_TYPE4_AUTOIDLE_SHIFT) + /* OCP SYSSTATUS bit shifts/masks */ #define SYSS_RESETDONE_SHIFT 0 #define SYSS_RESETDONE_MASK (1 << SYSS_RESETDONE_SHIFT) diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c index 79d623b..7443dc0 100644 --- a/arch/arm/mach-omap2/omap_hwmod_common_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c @@ -59,6 +59,16 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3 = { .sidle_shift = SYSC_TYPE3_SIDLEMODE_SHIFT, }; +/** + * struct omap_hwmod_sysc_type4 - TYPE4 sysconfig scheme. + * Used by some IPs on AM33xx + */ +struct omap_hwmod_sysc_fields omap_hwmod_sysc_type4 = { + .sidle_shift = SYSC_TYPE4_SIDLEMODE_SHIFT, + .srst_shift = SYSC_TYPE4_SOFTRESET_SHIFT, + .autoidle_shift = SYSC_TYPE4_AUTOIDLE_SHIFT, +}; + struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = { .manager_count = 2, .has_framedonetv_irq = 0