| Message ID | 1398658225-25873-5-git-send-email-george.cherian@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Apr 28, 2014 at 09:40:23AM +0530, George Cherian wrote: > Enable the Annex F Time Sync explicitly for DRA7x and AM4372. > With this enabled the L2 PTP is working. L2 works fine without this bit. If this is needed for V3 hardware, then it should have its own code variant. > while at that rename TS_BIT8 to TS_TTL_NONZERO Is this bit finally documented for am335x? Thanks, Richard -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 4/28/2014 1:25 PM, Richard Cochran wrote: > On Mon, Apr 28, 2014 at 09:40:23AM +0530, George Cherian wrote: >> Enable the Annex F Time Sync explicitly for DRA7x and AM4372. >> With this enabled the L2 PTP is working. > L2 works fine without this bit. If this is needed for V3 hardware, > then it should have its own code variant. okay > >> while at that rename TS_BIT8 to TS_TTL_NONZERO > Is this bit finally documented for am335x? Not for am335x, but for other SoC's it s documented. > Thanks, > Richard >
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index 085ffb5..af1423b 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -248,7 +248,8 @@ struct cpsw_ss_regs { #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ -#define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */ +#define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */ +#define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */ #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ @@ -256,8 +257,9 @@ struct cpsw_ss_regs { #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ #define CTRL_TS_BITS \ - (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \ - TS_ANNEX_D_EN | TS_LTYPE1_EN) + (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\ + TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\ + TS_LTYPE1_EN) #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN) #define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN)
Enable the Annex F Time Sync explicitly for DRA7x and AM4372. With this enabled the L2 PTP is working. while at that rename TS_BIT8 to TS_TTL_NONZERO Signed-off-by: George Cherian <george.cherian@ti.com> --- drivers/net/ethernet/ti/cpsw.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)