From patchwork Tue Apr 29 20:19:50 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 4089031 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id AFAAB9F4F4 for ; Tue, 29 Apr 2014 20:20:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EE3D920222 for ; Tue, 29 Apr 2014 20:20:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 11CE3201CE for ; Tue, 29 Apr 2014 20:20:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758435AbaD2UUg (ORCPT ); Tue, 29 Apr 2014 16:20:36 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:44075 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758419AbaD2UUf (ORCPT ); Tue, 29 Apr 2014 16:20:35 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id s3TKJxTa008152; Tue, 29 Apr 2014 15:19:59 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3TKJxTg002464; Tue, 29 Apr 2014 15:19:59 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.174.1; Tue, 29 Apr 2014 15:19:58 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3TKJx6Y030856; Tue, 29 Apr 2014 15:19:59 -0500 Received: from localhost (j-172-22-136-12.vpn.ti.com [172.22.136.12]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id s3TKJwt25423; Tue, 29 Apr 2014 15:19:58 -0500 (CDT) From: Dan Murphy To: , , , CC: , , , Dan Murphy Subject: [RFC 11/11] ARM: dts: omap5: Add prm_resets node Date: Tue, 29 Apr 2014 15:19:50 -0500 Message-ID: <1398802790-29287-12-git-send-email-dmurphy@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1398802790-29287-1-git-send-email-dmurphy@ti.com> References: <1398802790-29287-1-git-send-email-dmurphy@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the prm_resets node to the prm parent node. Add the dt-bindings header to the DT file Signed-off-by: Dan Murphy --- arch/arm/boot/dts/omap5.dtsi | 6 ++++++ include/dt-bindings/reset/ti,omap5-resets.h | 22 ++++++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 include/dt-bindings/reset/ti,omap5-resets.h diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index f8c9855..82eebe7 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include "skeleton.dtsi" @@ -134,6 +135,11 @@ prm_clockdomains: clockdomains { }; + + prm_resets: resets { + compatible = "ti,omap5-resets"; + #reset-cells = <1>; + }; }; cm_core_aon: cm_core_aon@4a004000 { diff --git a/include/dt-bindings/reset/ti,omap5-resets.h b/include/dt-bindings/reset/ti,omap5-resets.h new file mode 100644 index 0000000..33bb295 --- /dev/null +++ b/include/dt-bindings/reset/ti,omap5-resets.h @@ -0,0 +1,22 @@ +/* + * OMAP5 reset index for PRCM Module + * + * Copyright 2014 Texas Instruments Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _DT_BINDINGS_RESET_TI_OMAP5_H +#define _DT_BINDINGS_RESET_TI_OMAP5_H + +#define RESET_DEVICE_RESET 0 +#define RESET_DSP_RESET 1 +#define RESET_DSP_MMU_CACHE_RESET 2 +#define RESET_IPU_CPU0_RESET 3 +#define RESET_IPU_CPU1_RESET 4 +#define RESET_IPU_MMU_CACHE_RESET 5 +#define RESET_IVA_RESET 6 + +#endif