From patchwork Tue Apr 29 20:19:47 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 4089001 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 91203BFF02 for ; Tue, 29 Apr 2014 20:20:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9AEBB201C0 for ; Tue, 29 Apr 2014 20:20:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A7C8B20222 for ; Tue, 29 Apr 2014 20:20:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758412AbaD2UUe (ORCPT ); Tue, 29 Apr 2014 16:20:34 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:44071 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758373AbaD2UUa (ORCPT ); Tue, 29 Apr 2014 16:20:30 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s3TKJvx8010926; Tue, 29 Apr 2014 15:19:57 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3TKJvuE024471; Tue, 29 Apr 2014 15:19:57 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Tue, 29 Apr 2014 15:19:57 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3TKJvsg030803; Tue, 29 Apr 2014 15:19:57 -0500 Received: from localhost (j-172-22-136-12.vpn.ti.com [172.22.136.12]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id s3TKJut25411; Tue, 29 Apr 2014 15:19:56 -0500 (CDT) From: Dan Murphy To: , , , CC: , , , Dan Murphy Subject: [RFC 08/11] ARM: dts: am33xx: Add prcm_resets node Date: Tue, 29 Apr 2014 15:19:47 -0500 Message-ID: <1398802790-29287-9-git-send-email-dmurphy@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1398802790-29287-1-git-send-email-dmurphy@ti.com> References: <1398802790-29287-1-git-send-email-dmurphy@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the prcm_resets node to the prcm parent node. Add the dt-bindings header to the DT file Signed-off-by: Dan Murphy --- arch/arm/boot/dts/am33xx.dtsi | 6 ++++++ include/dt-bindings/reset/ti,am33xx-resets.h | 18 ++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 include/dt-bindings/reset/ti,am33xx-resets.h diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 07f283c..df9d9c6 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -10,6 +10,7 @@ #include #include +#include #include "skeleton.dtsi" @@ -117,6 +118,11 @@ prcm_clockdomains: clockdomains { }; + + prcm_resets: resets { + compatible = "ti,am335x-resets"; + #reset-cells = <1>; + }; }; scrm: scrm@44e10000 { diff --git a/include/dt-bindings/reset/ti,am33xx-resets.h b/include/dt-bindings/reset/ti,am33xx-resets.h new file mode 100644 index 0000000..dfe7954 --- /dev/null +++ b/include/dt-bindings/reset/ti,am33xx-resets.h @@ -0,0 +1,18 @@ +/* + * AM33xx reset index for PRCM Module + * + * Copyright 2014 Texas Instruments Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _DT_BINDINGS_RESET_TI_AM33XX_H +#define _DT_BINDINGS_RESET_TI_AM33XX_H + +#define RESET_DEVICE_RESET 0 +#define RESET_GFX_RESET 1 +#define RESET_PER_RESET 2 + +#endif