From patchwork Wed Apr 30 02:53:47 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Fernandes X-Patchwork-Id: 4090891 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 0F4319F271 for ; Wed, 30 Apr 2014 02:54:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F1C9C20211 for ; Wed, 30 Apr 2014 02:54:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CA1F020170 for ; Wed, 30 Apr 2014 02:54:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753794AbaD3Cy3 (ORCPT ); Tue, 29 Apr 2014 22:54:29 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:60996 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753305AbaD3Cy2 (ORCPT ); Tue, 29 Apr 2014 22:54:28 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id s3U2rrCt018108; Tue, 29 Apr 2014 21:53:53 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3U2rrMs005887; Tue, 29 Apr 2014 21:53:53 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.174.1; Tue, 29 Apr 2014 21:53:53 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3U2rrxm023266; Tue, 29 Apr 2014 21:53:53 -0500 Received: from joel-laptop.itg.ti.com (j-172-22-157-56.vpn.ti.com [172.22.157.56]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id s3U2rpt19442; Tue, 29 Apr 2014 21:53:52 -0500 (CDT) From: Joel Fernandes To: Tony Lindgren CC: Joel Fernandes , Dave Martin , Santosh Shilimkar , Russell King , Nishanth Menon , "open list:OMAP SUPPORT" , "moderated list:ARM SUB-ARCHITECT..." , open list Subject: [PATCH] ARM: OMAP5: Redo THUMB mode switch on secondary CPU Date: Tue, 29 Apr 2014 21:53:47 -0500 Message-ID: <1398826427-17200-1-git-send-email-joelf@ti.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Here's a redo of the patch [1] that effectively does the same thing but is the right way to do things by using ENDPROC instead. The firmware correctly switches to THUMB before entry. The patch applies ontop of the earlier patch [1]. [1] https://lkml.org/lkml/2014/4/22/1044 Suggested-by: Dave Martin Cc: Dave Martin Cc: Santosh Shilimkar Cc: Russell King Cc: Nishanth Menon Cc: Tony Lindgren Signed-off-by: Joel Fernandes Reviewed-by: Dave Martin --- Tony, the earlier patch went into your fixes, and can remain. This patch is just a simple redo of the same and can go in for v3.16, no problem. Thanks. arch/arm/mach-omap2/omap-headsmp.S | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S index 1809dce..bf36f26 100644 --- a/arch/arm/mach-omap2/omap-headsmp.S +++ b/arch/arm/mach-omap2/omap-headsmp.S @@ -31,10 +31,6 @@ * register AuxCoreBoot0. */ ENTRY(omap5_secondary_startup) -.arm -THUMB( adr r9, BSYM(wait) ) @ CPU may be entered in ARM mode. -THUMB( bx r9 ) @ If this is a Thumb-2 kernel, -THUMB( .thumb ) @ switch to Thumb now. wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 ldr r0, [r2] mov r0, r0, lsr #5 @@ -43,7 +39,7 @@ wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 cmp r0, r4 bne wait b secondary_startup -END(omap5_secondary_startup) +ENDPROC(omap5_secondary_startup) /* * OMAP4 specific entry point for secondary CPU to jump from ROM * code. This routine also provides a holding flag into which