From patchwork Mon May 5 20:09:23 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 4116961 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1DE9D9F23C for ; Mon, 5 May 2014 20:10:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 39E0E20254 for ; Mon, 5 May 2014 20:10:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 24AB22022A for ; Mon, 5 May 2014 20:10:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753988AbaEEUJ7 (ORCPT ); Mon, 5 May 2014 16:09:59 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:48460 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752341AbaEEUJz (ORCPT ); Mon, 5 May 2014 16:09:55 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id s45K9VN9013591; Mon, 5 May 2014 15:09:31 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s45K9VnN025142; Mon, 5 May 2014 15:09:31 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Mon, 5 May 2014 15:09:31 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s45K9VrV007819; Mon, 5 May 2014 15:09:31 -0500 Received: from localhost (j-172-22-140-142.vpn.ti.com [172.22.140.142]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id s45K9Vt09738; Mon, 5 May 2014 15:09:31 -0500 (CDT) From: Dan Murphy To: , , , CC: Dan Murphy Subject: [RFC] [v2 Patch 2/6] ARM: TI: Describe the ti reset DT entries Date: Mon, 5 May 2014 15:09:23 -0500 Message-ID: <1399320567-3639-3-git-send-email-dmurphy@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1399320567-3639-1-git-send-email-dmurphy@ti.com> References: <1399320567-3639-1-git-send-email-dmurphy@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Describe the TI reset DT entries for TI SoC's. Signed-off-by: Dan Murphy --- .../devicetree/bindings/reset/ti,reset.txt | 103 ++++++++++++++++++++ 1 file changed, 103 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/ti,reset.txt diff --git a/Documentation/devicetree/bindings/reset/ti,reset.txt b/Documentation/devicetree/bindings/reset/ti,reset.txt new file mode 100644 index 0000000..9d5c29c --- /dev/null +++ b/Documentation/devicetree/bindings/reset/ti,reset.txt @@ -0,0 +1,103 @@ +Texas Instruments Reset Controller +====================================== +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Specifying the reset entries for the IP module +============================================== +Parent module: +This is the module node that contains the reset registers and bits. + +example: + prcm_resets: resets { + compatible = "ti,dra7-resets"; + #reset-cells = <1>; + }; + +Required parent properties: +- compatible : Should be one of, + "ti,omap4-prm" for OMAP4 PRM instances + "ti,omap5-prm" for OMAP5 PRM instances + "ti,dra7-prm" for DRA7xx PRM instances + "ti,am4-prcm" for AM43xx PRCM instances + "ti,am3-prcm" for AM33xx PRCM instances + +Required child reset property: +- compatible : Should be + "resets" for All TI SoCs + +example: + prm: prm@4ae06000 { + compatible = "ti,omap5-prm"; + reg = <0x4ae06000 0x3000>; + + prm_resets: resets { + #address-cells = <1>; + #size-cells = <1>; + #reset-cells = <1>; + }; + }; + + +Reset node declaration +============================================== +The reset node is declared in a parent child relationship. The main parent +is the PRCM module which contains the base address. The first child within +the reset parent declares the target modules reset name. This is followed by +the control and status offsets. + +Within the first reset child node is a secondary child node which declares the +reset signal of interest. Under this node the control and status bits +are declared. These bits declare the bit mask for the target reset. + + +Required properties: +reg - This is the register offset from the PRCM parent. + This must be declared as: + + reg = , + ; + +control-bit - This is the bit within the register which controls the reset + of the target module. This is declared as a bit mask for the register. +status-bit - This is the bit within the register which contains the status of + the reset of the target module. + This is declared as a bit mask for the register. + +example: +&prm_resets { + dsp_rstctrl { + reg = <0x1c00>, + <0x1c04>; + + dsp_reset: dsp_reset { + control-bit = <0x01>; + status-bit = <0x01>; + }; + }; +}; + + + +Client Node Declaration +============================================== +This is the consumer of the parent node to declare what resets this +particular module is interested in. + +example: + src: src@55082000 { + resets = <&reset_src phandle>; + reset-names = ""; + }; + +Required Properties: +reset_src - This is the parent DT entry for the reset controller +phandle - This is the phandle of the specific reset to be used by the clien + driver. +reset-names - This is the reset name of module that the device driver + needs to be able to reset. This value must correspond to a value within + the reset controller array. + +example: +resets = <&prm_resets &dsp_mmu_reset>; +reset-names = "dsp_mmu_reset";