From patchwork Thu May 8 23:20:33 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andreas Fenkart X-Patchwork-Id: 4139481 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2047D9F391 for ; Thu, 8 May 2014 23:21:37 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5133220035 for ; Thu, 8 May 2014 23:21:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7EC9D202DD for ; Thu, 8 May 2014 23:21:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932109AbaEHXVd (ORCPT ); Thu, 8 May 2014 19:21:33 -0400 Received: from mail-ee0-f42.google.com ([74.125.83.42]:33708 "EHLO mail-ee0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932080AbaEHXVc (ORCPT ); Thu, 8 May 2014 19:21:32 -0400 Received: by mail-ee0-f42.google.com with SMTP id d49so2101415eek.15 for ; Thu, 08 May 2014 16:21:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=E+vjpuywYok1MLYD37QqFPb5Hyl2mU13EAoD2cw0CMQ=; b=teT73NL+F+q2IpjCI61pEQMbwM3xQZg5uiA43FU1caMQL2hejSNRyo/1nlkThCHjP7 XvVxi+sUG2BUlrjaraoxQm2ouUVwLSPxUIyQ4A18NH12CaBsURf3bKMkS/IpRubZs+s3 xeTySi4miXmX6f7E2jDokhU4JZNfEf+5zj3VTbyLdbKDWNYtrzSuw3+3TaLzsL/P7t7T MrhmHQIQyMdIWQdc2UXCw+jnXhUJR9J1KXloLirY7D6j+BE8sWhrmXOo25f3B/hJsMdH 7EEfWCL0wyd1Pn515/wKzaMsFnnLRozUQblnfKtSjuGveJh+AaIJNVfvHdHMknzj2RMA E+2g== X-Received: by 10.15.83.68 with SMTP id b44mr8715659eez.11.1399591291325; Thu, 08 May 2014 16:21:31 -0700 (PDT) Received: from localhost (13-242.62-81.cust.bluewin.ch. [81.62.242.13]) by mx.google.com with ESMTPSA id t4sm7312629eeb.29.2014.05.08.16.21.29 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 08 May 2014 16:21:30 -0700 (PDT) From: Andreas Fenkart To: Tony Lindgren Cc: Chris Ball , Grant Likely , Felipe Balbi , Balaji T K , Andreas Mueller , zonque@gmail.com, galak@codeaurora.org, linux-doc@vger.kernel.org, linux-mmc@vger.kernel.org, linux-omap@vger.kernel.org, Andreas Fenkart Subject: [PATCH v11 6/7] mmc: omap_hsmmc: switch default/idle pinctrl states in runtime hooks Date: Fri, 9 May 2014 01:20:33 +0200 Message-Id: <1399591234-13089-6-git-send-email-afenkart@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1399591234-13089-1-git-send-email-afenkart@gmail.com> References: <1399591018-12930-1-git-send-email-afenkart@gmail.com> <1399591234-13089-1-git-send-email-afenkart@gmail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP These are predefined states of the driver model. When not present, as if not set in the device tree, they become no-ops. Explicitly selecting the default state is not needed since the device core layer sets pin mux to "default" state before probe. This is not the simplest implementation, on AM335x at least, we could switch to idle at any point in the suspend hook, only the default state needs to be set before writing to the irq registers or an IRQ might get lost. Signed-off-by: Andreas Fenkart Acked-by: Balaji T K diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index 47a5982..5a321f98 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -2032,7 +2032,6 @@ static int omap_hsmmc_probe(struct platform_device *pdev) const struct of_device_id *match; dma_cap_mask_t mask; unsigned tx_req, rx_req; - struct pinctrl *pinctrl; const struct omap_mmc_of_data *data; apply_clk_hack(&pdev->dev); @@ -2258,11 +2257,6 @@ static int omap_hsmmc_probe(struct platform_device *pdev) omap_hsmmc_disable_irq(host); - pinctrl = devm_pinctrl_get_select_default(&pdev->dev); - if (IS_ERR(pinctrl)) - dev_warn(&pdev->dev, - "pins are not configured from the driver\n"); - /* * For now, only support SDIO interrupt if we have a separate * wake-up interrupt configured from device tree. This is because @@ -2486,10 +2480,15 @@ static int omap_hsmmc_runtime_suspend(struct device *dev) goto abort; } + pinctrl_pm_select_idle_state(dev); + WARN_ON(host->flags & HSMMC_WAKE_IRQ_ENABLED); enable_irq(host->wake_irq); host->flags |= HSMMC_WAKE_IRQ_ENABLED; + } else { + pinctrl_pm_select_idle_state(dev); } + abort: spin_unlock_irqrestore(&host->irq_lock, flags); return ret; @@ -2513,9 +2512,14 @@ static int omap_hsmmc_runtime_resume(struct device *dev) host->flags &= ~HSMMC_WAKE_IRQ_ENABLED; } + pinctrl_pm_select_default_state(host->dev); + + /* irq lost, if pinmux incorrect */ OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); + } else { + pinctrl_pm_select_default_state(host->dev); } spin_unlock_irqrestore(&host->irq_lock, flags); return 0;