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[46.246.40.223]) by mx.google.com with ESMTPSA id z1sm934544lal.6.2014.05.22.16.06.57 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 22 May 2014 16:06:59 -0700 (PDT) From: Christoph Fritz To: Tony Lindgren , Grygorii Strashko , Pekon Gupta , =?UTF-8?q?Beno=C3=AEt=20Cousson?= Cc: Daniel Mack , linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/5] [RFC] ARM: OMAP2+: gpmc: fix gpmc_hwecc_bch_capable Date: Fri, 23 May 2014 01:06:25 +0200 Message-Id: <1400799986-20043-5-git-send-email-chf.fritz@googlemail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1400799986-20043-1-git-send-email-chf.fritz@googlemail.com> References: <1400799986-20043-1-git-send-email-chf.fritz@googlemail.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Most dt omap3 boards configure nand-ecc-opt as bch8. Due to lack of hardware elm support, bch8 software implementation gets set. Since commit 0611c41934ab35ce84dea "ARM: OMAP2+: gpmc: update gpmc_hwecc_bch_capable() for new platforms and ECC schemes", nand support stops working. This patch allows ecc software fallback. --- arch/arm/mach-omap2/gpmc-nand.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index 4349e82..52c4834 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c @@ -43,13 +43,17 @@ static struct platform_device gpmc_nand_device = { .resource = gpmc_nand_resource, }; -static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) +static bool gpmc_ecc_bch_capable(enum omap_ecc ecc_opt) { /* platforms which support all ECC schemes */ if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) return 1; + if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW) || + (ecc_opt == OMAP_ECC_BCH8_CODE_HW_DETECTION_SW)) + return 1; + /* OMAP3xxx do not have ELM engine, so cannot support ECC schemes * which require H/W based ECC error detection */ if ((cpu_is_omap34xx() || cpu_is_omap3630()) && @@ -57,14 +61,6 @@ static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) (ecc_opt == OMAP_ECC_BCH8_CODE_HW))) return 0; - /* - * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1 - * and AM33xx derivates. Other chips may be added if confirmed to work. - */ - if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW) && - (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) - return 0; - /* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */ if (ecc_opt == OMAP_ECC_HAM1_CODE_HW) return 1; @@ -140,7 +136,7 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); - if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) { + if (!gpmc_ecc_bch_capable(gpmc_nand_data->ecc_opt)) { dev_err(dev, "Unsupported NAND ECC scheme selected\n"); return -EINVAL; }