@@ -592,7 +592,27 @@ static struct of_device_id omap_scrm_dt_match_table[] = {
{ }
};
-int __init of_scrm_init(void)
+static int __init of_scrm_init(void)
{
return of_prcm_module_init(omap_scrm_dt_match_table);
}
+
+static struct of_device_id omap_ctrl_core_dt_match_table[] = {
+ { .compatible = "ti,dra7-ctrl-core" },
+ { }
+};
+
+static int __init of_ctrl_core_init(void)
+{
+ return of_prcm_module_init(omap_ctrl_core_dt_match_table);
+}
+
+int __init of_control_init(void)
+{
+ int ret;
+
+ ret = of_scrm_init();
+ ret |= of_ctrl_core_init();
+
+ return ret;
+}
@@ -428,7 +428,7 @@ extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
extern void omap3630_ctrl_disable_rta(void);
extern int omap3_ctrl_save_padconf(void);
extern void omap3_ctrl_set_iva_bootmode_idle(void);
-int of_scrm_init(void);
+int of_control_init(void);
extern void omap2_set_globals_control(void __iomem *ctrl,
void __iomem *ctrl_pad);
#else
@@ -725,7 +725,7 @@ int __init omap_clk_init(void)
if (!omap_clk_soc_init)
return 0;
- ret = of_scrm_init();
+ ret = of_control_init();
if (ret)
return ret;
In DRA7x SoCs, the CONTROL_MODULE_CORE sub block in the control module has a few register fields which perform gating or muxing of clocks. These gate/muxes are generally SoC level clocks entering an IP, which didn't manage to make it in the clock management related registers for the IP. Other OMAP SOCs don't seem to have clock related register fields in the control module. We create a new table and function to init ctrl-core IPS as clock providers. This, along with scrm clock providers, are initialized in of_control_init(). We add a compatible string for dra7-ctrl-core in the DT match table. Signed-off-by: Archit Taneja <archit@ti.com> --- arch/arm/mach-omap2/control.c | 22 +++++++++++++++++++++- arch/arm/mach-omap2/control.h | 2 +- arch/arm/mach-omap2/io.c | 2 +- 3 files changed, 23 insertions(+), 3 deletions(-)