From patchwork Wed May 28 10:50:52 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: archit taneja X-Patchwork-Id: 4254491 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1D1029F336 for ; Wed, 28 May 2014 10:52:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 557D820279 for ; Wed, 28 May 2014 10:52:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 72E0D2026C for ; Wed, 28 May 2014 10:52:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752169AbaE1Kwa (ORCPT ); Wed, 28 May 2014 06:52:30 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:37318 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752098AbaE1Kw3 (ORCPT ); Wed, 28 May 2014 06:52:29 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id s4SAqSUj004993; Wed, 28 May 2014 05:52:28 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s4SAqSr8001877; Wed, 28 May 2014 05:52:28 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.174.1; Wed, 28 May 2014 05:52:27 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s4SAqRrv030390; Wed, 28 May 2014 05:52:27 -0500 Received: from localhost (a0393947pc.apr.dhcp.ti.com [172.24.145.166]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id s4SAqPt20001; Wed, 28 May 2014 05:52:26 -0500 (CDT) From: Archit Taneja To: , , CC: , Archit Taneja Subject: [RFC v2 3/6] ARM: OMAP2+: Add CONTROL_MODULE_CORE as a clock provider for DRA7x Date: Wed, 28 May 2014 16:20:52 +0530 Message-ID: <1401274255-16845-4-git-send-email-archit@ti.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1401274255-16845-1-git-send-email-archit@ti.com> References: <1397654063-8055-1-git-send-email-archit@ti.com> <1401274255-16845-1-git-send-email-archit@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In DRA7x SoCs, the CONTROL_MODULE_CORE sub block in the control module has a few register fields which perform gating or muxing of clocks. These gate/muxes are generally SoC level clocks entering an IP, which didn't manage to make it in the clock management related registers for the IP. Other OMAP SOCs don't seem to have clock related register fields in the control module. We create a new table and function to init ctrl-core IPS as clock providers. This, along with scrm clock providers, are initialized in of_control_init(). We add a compatible string for dra7-ctrl-core in the DT match table. Signed-off-by: Archit Taneja --- arch/arm/mach-omap2/control.c | 22 +++++++++++++++++++++- arch/arm/mach-omap2/control.h | 2 +- arch/arm/mach-omap2/io.c | 2 +- 3 files changed, 23 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 12cd736..d9567bc 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -592,7 +592,27 @@ static struct of_device_id omap_scrm_dt_match_table[] = { { } }; -int __init of_scrm_init(void) +static int __init of_scrm_init(void) { return of_prcm_module_init(omap_scrm_dt_match_table); } + +static struct of_device_id omap_ctrl_core_dt_match_table[] = { + { .compatible = "ti,dra7-ctrl-core" }, + { } +}; + +static int __init of_ctrl_core_init(void) +{ + return of_prcm_module_init(omap_ctrl_core_dt_match_table); +} + +int __init of_control_init(void) +{ + int ret; + + ret = of_scrm_init(); + ret |= of_ctrl_core_init(); + + return ret; +} diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index 5d695f1..405979e 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -428,7 +428,7 @@ extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode); extern void omap3630_ctrl_disable_rta(void); extern int omap3_ctrl_save_padconf(void); extern void omap3_ctrl_set_iva_bootmode_idle(void); -int of_scrm_init(void); +int of_control_init(void); extern void omap2_set_globals_control(void __iomem *ctrl, void __iomem *ctrl_pad); #else diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index c78e2b8..49e344b 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -725,7 +725,7 @@ int __init omap_clk_init(void) if (!omap_clk_soc_init) return 0; - ret = of_scrm_init(); + ret = of_control_init(); if (ret) return ret;