From patchwork Wed May 28 10:50:55 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: archit taneja X-Patchwork-Id: 4254521 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E0B2F9F336 for ; Wed, 28 May 2014 10:52:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2742720279 for ; Wed, 28 May 2014 10:52:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 444A22026C for ; Wed, 28 May 2014 10:52:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752524AbaE1Kwi (ORCPT ); Wed, 28 May 2014 06:52:38 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:34483 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752387AbaE1Kwi (ORCPT ); Wed, 28 May 2014 06:52:38 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id s4SAqbbu032132; Wed, 28 May 2014 05:52:37 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s4SAqb45008497; Wed, 28 May 2014 05:52:37 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.174.1; Wed, 28 May 2014 05:52:36 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s4SAqbU7030452; Wed, 28 May 2014 05:52:37 -0500 Received: from localhost (a0393947pc.apr.dhcp.ti.com [172.24.145.166]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id s4SAqZt20030; Wed, 28 May 2014 05:52:35 -0500 (CDT) From: Archit Taneja To: , , CC: , Archit Taneja Subject: [RFC v2 6/6] CLK: TI: Enable dss_deshdcp clock in dra7xx_clk_init Date: Wed, 28 May 2014 16:20:55 +0530 Message-ID: <1401274255-16845-7-git-send-email-archit@ti.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1401274255-16845-1-git-send-email-archit@ti.com> References: <1397654063-8055-1-git-send-email-archit@ti.com> <1401274255-16845-1-git-send-email-archit@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The DESHDCP clock is required only by the DES-HDCP block within HDMI in DSS. However, if the clock isn't set before DSS clock domian is enabled, the clock domain never comes out of idle state. This is because the DSS IP is designed in such a way that if DES-HDCP block can't transition from idle state, the entire DSS clock domain also cannot transition from idle to enabled. DES-HDCP block needs the DESHDCP clock enabled to transition from idle successfully. We enable the deshdcp clock in dra7xx_clk_init() which happens before omap hwmods are setup. This clock is effectively a gate clock with the parent as DSS_L3_GICLK. The parent is an automatically controlled clock by DSS clock domain and hence doesn't have a clock node associated to it. Since DSS_L3_GICLK is derived from the OCP clock, we set the dss_deshdcp_clk's parent as l3_iclk_div. Leaving this bit enabled doesn't prevent DSS or the system to suspend, and only a very few flops get this clock all the time. So there is negligible impact. Signed-off-by: Archit Taneja --- drivers/clk/ti/clk-7xx.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index f7e4073..3f73a02 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c @@ -179,6 +179,7 @@ static struct ti_dt_clk dra7xx_clks[] = { DT_CLK(NULL, "dss_hdmi_clk", "dss_hdmi_clk"), DT_CLK(NULL, "dss_video1_clk", "dss_video1_clk"), DT_CLK(NULL, "dss_video2_clk", "dss_video2_clk"), + DT_CLK(NULL, "dss_deshdcp_clk", "dss_deshdcp_clk"), DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), @@ -306,7 +307,7 @@ static struct ti_dt_clk dra7xx_clks[] = { int __init dra7xx_dt_clk_init(void) { int rc; - struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck; + struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck, *dss_deshdcp_ck; ti_dt_clocks_register(dra7xx_clks); @@ -327,5 +328,10 @@ int __init dra7xx_dt_clk_init(void) if (rc) pr_err("%s: failed to configure GMAC DPLL!\n", __func__); + dss_deshdcp_ck = clk_get_sys(NULL, "dss_deshdcp_clk"); + rc = clk_prepare_enable(dss_deshdcp_ck); + if (rc) + pr_err("%s: failed to enable DESHDCP clock\n", __func__); + return rc; }