From patchwork Wed Jul 9 05:36:27 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "J, KEERTHY" X-Patchwork-Id: 4511771 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3FABFBEEAA for ; Wed, 9 Jul 2014 05:41:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7839A2021F for ; Wed, 9 Jul 2014 05:41:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3B8ED202E5 for ; Wed, 9 Jul 2014 05:41:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752831AbaGIFiu (ORCPT ); Wed, 9 Jul 2014 01:38:50 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:40671 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752020AbaGIFim (ORCPT ); Wed, 9 Jul 2014 01:38:42 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id s695cUJA027137; Wed, 9 Jul 2014 00:38:30 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s695cUU4030576; Wed, 9 Jul 2014 00:38:30 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Wed, 9 Jul 2014 00:38:30 -0500 Received: from ula0393675.apr.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s695cLTe014950; Wed, 9 Jul 2014 00:38:26 -0500 From: Keerthy To: , , CC: , , , , , , , , Keerthy Subject: [PATCH v3 1/7] regulator: tps65218: Add fixed_uV fields for dcdc5 and dcdc6 Date: Wed, 9 Jul 2014 11:06:27 +0530 Message-ID: <1404884193-20580-2-git-send-email-j-keerthy@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1404884193-20580-1-git-send-email-j-keerthy@ti.com> References: <1404884193-20580-1-git-send-email-j-keerthy@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add fixed_uV fields for dcdc5 and dcdc6. Signed-off-by: Keerthy --- Changes from V2: * Added fixed_uV fields for the regulator_desc structures. drivers/regulator/tps65218-regulator.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/regulator/tps65218-regulator.c b/drivers/regulator/tps65218-regulator.c index 9effe48..27dc70d 100644 --- a/drivers/regulator/tps65218-regulator.c +++ b/drivers/regulator/tps65218-regulator.c @@ -30,7 +30,7 @@ enum tps65218_regulators { DCDC1, DCDC2, DCDC3, DCDC4, DCDC5, DCDC6, LDO1 }; #define TPS65218_REGULATOR(_name, _id, _ops, _n, _vr, _vm, _er, _em, _t, \ - _lr, _nlr, _delay) \ + _lr, _nlr, _delay, _fuv) \ { \ .name = _name, \ .id = _id, \ @@ -46,6 +46,7 @@ enum tps65218_regulators { DCDC1, DCDC2, DCDC3, DCDC4, DCDC5, DCDC6, LDO1 }; .linear_ranges = _lr, \ .n_linear_ranges = _nlr, \ .ramp_delay = _delay, \ + .fixed_uV = _fuv \ } \ #define TPS65218_INFO(_id, _nm, _min, _max) \ @@ -186,33 +187,33 @@ static const struct regulator_desc regulators[] = { TPS65218_REG_CONTROL_DCDC1, TPS65218_CONTROL_DCDC1_MASK, TPS65218_REG_ENABLE1, TPS65218_ENABLE1_DC1_EN, NULL, - dcdc1_dcdc2_ranges, 2, 4000), + dcdc1_dcdc2_ranges, 2, 4000, 0), TPS65218_REGULATOR("DCDC2", TPS65218_DCDC_2, tps65218_dcdc12_ops, 64, TPS65218_REG_CONTROL_DCDC2, TPS65218_CONTROL_DCDC2_MASK, TPS65218_REG_ENABLE1, TPS65218_ENABLE1_DC2_EN, NULL, - dcdc1_dcdc2_ranges, 2, 4000), + dcdc1_dcdc2_ranges, 2, 4000, 0), TPS65218_REGULATOR("DCDC3", TPS65218_DCDC_3, tps65218_ldo1_dcdc34_ops, 64, TPS65218_REG_CONTROL_DCDC3, TPS65218_CONTROL_DCDC3_MASK, TPS65218_REG_ENABLE1, TPS65218_ENABLE1_DC3_EN, NULL, - ldo1_dcdc3_ranges, 2, 0), + ldo1_dcdc3_ranges, 2, 0, 0), TPS65218_REGULATOR("DCDC4", TPS65218_DCDC_4, tps65218_ldo1_dcdc34_ops, 53, TPS65218_REG_CONTROL_DCDC4, TPS65218_CONTROL_DCDC4_MASK, TPS65218_REG_ENABLE1, TPS65218_ENABLE1_DC4_EN, NULL, - dcdc4_ranges, 2, 0), + dcdc4_ranges, 2, 0, 0), TPS65218_REGULATOR("DCDC5", TPS65218_DCDC_5, tps65218_dcdc56_pmic_ops, 1, -1, -1, TPS65218_REG_ENABLE1, - TPS65218_ENABLE1_DC5_EN, NULL, NULL, 0, 0), + TPS65218_ENABLE1_DC5_EN, NULL, NULL, 0, 0, 1000000), TPS65218_REGULATOR("DCDC6", TPS65218_DCDC_6, tps65218_dcdc56_pmic_ops, 1, -1, -1, TPS65218_REG_ENABLE1, - TPS65218_ENABLE1_DC6_EN, NULL, NULL, 0, 0), + TPS65218_ENABLE1_DC6_EN, NULL, NULL, 0, 0, 1800000), TPS65218_REGULATOR("LDO1", TPS65218_LDO_1, tps65218_ldo1_dcdc34_ops, 64, TPS65218_REG_CONTROL_LDO1, TPS65218_CONTROL_LDO1_MASK, TPS65218_REG_ENABLE2, TPS65218_ENABLE2_LDO1_EN, NULL, ldo1_dcdc3_ranges, - 2, 0), + 2, 0, 0), }; static int tps65218_regulator_probe(struct platform_device *pdev)