From patchwork Wed Jul 9 05:36:28 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "J, KEERTHY" X-Patchwork-Id: 4511721 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B2C4F9F39B for ; Wed, 9 Jul 2014 05:40:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E6EAA202B4 for ; Wed, 9 Jul 2014 05:40:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 158812021F for ; Wed, 9 Jul 2014 05:40:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753166AbaGIFiw (ORCPT ); Wed, 9 Jul 2014 01:38:52 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:44666 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752051AbaGIFio (ORCPT ); Wed, 9 Jul 2014 01:38:44 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id s695cYfd010877; Wed, 9 Jul 2014 00:38:34 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s695cYqt030825; Wed, 9 Jul 2014 00:38:34 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.174.1; Wed, 9 Jul 2014 00:38:33 -0500 Received: from ula0393675.apr.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s695cLTf014950; Wed, 9 Jul 2014 00:38:30 -0500 From: Keerthy To: , , CC: , , , , , , , , Keerthy Subject: [PATCH v3 2/7] mfd: Add DT bindings for tps65218 PMIC Date: Wed, 9 Jul 2014 11:06:28 +0530 Message-ID: <1404884193-20580-3-git-send-email-j-keerthy@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1404884193-20580-1-git-send-email-j-keerthy@ti.com> References: <1404884193-20580-1-git-send-email-j-keerthy@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add DT bindings for tps65218 PMIC Signed-off-by: Keerthy Reviewed-by: Felipe Balbi --- Documentation/devicetree/bindings/mfd/tps65218.txt | 89 ++++++++++++++++++++ 1 file changed, 89 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/tps65218.txt diff --git a/Documentation/devicetree/bindings/mfd/tps65218.txt b/Documentation/devicetree/bindings/mfd/tps65218.txt new file mode 100644 index 0000000..01ac973 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/tps65218.txt @@ -0,0 +1,89 @@ +Texas Instruments TPS65218 family + +The TPS65218 are Integrated Power Management Chips. + +Required properties: +- compatible : Must be "ti,tps65218"; + For Integrated power-management used in AM437x based boards +- interrupts : This i2c device has an IRQ line connected to the main SoC +- interrupt-controller : Since the tps65218 supports several interrupts + internally, it is considered as an interrupt controller cascaded to the + SoC one. +- #interrupt-cells = <2>; +- interrupt-parent : The parent interrupt controller which is gic. + +Optional node: +- TPS65218 PMIC has a number of child nodes. Mainly the regularors and SMPSs. + +Example: +/* + * Integrated Power Management Chip + */ +tps65218: tps65218@24 { + reg = <0x24>; + compatible = "ti,tps65218"; + interrupts = ; /* NMIn */ + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + + dcdc1: regulator-dcdc1 { + compatible = "ti,tps65218-dcdc1"; + /* VDD_CORE voltage limits min of OPP50 and max of OPP100 */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc2: regulator-dcdc2 { + compatible = "ti,tps65218-dcdc2"; + /* VDD_MPU voltage limits min of OPP50 and max of OPP_NITRO */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <1378000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3: regulator-dcdc3 { + compatible = "ti,tps65218-dcdc3"; + regulator-name = "vdcdc3"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc4: regulator-dcdc4 { + compatible = "ti,tps65218-dcdc4"; + regulator-name = "v3_3d"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc5: regulator-dcdc5 { + compatible = "ti,tps65218-dcdc5"; + regulator-name = "v1_0bat"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + dcdc6: regulator-dcdc6 { + compatible = "ti,tps65218-dcdc6"; + regulator-name = "v1_8vat"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo1: regulator-ldo1 { + compatible = "ti,tps65218-ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; +};