From patchwork Thu Jul 17 16:45:29 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 4577481 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D946EC0514 for ; Thu, 17 Jul 2014 16:46:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 246502010B for ; Thu, 17 Jul 2014 16:46:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A3987201BB for ; Thu, 17 Jul 2014 16:46:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934273AbaGQQqL (ORCPT ); Thu, 17 Jul 2014 12:46:11 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:42453 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757457AbaGQQqA (ORCPT ); Thu, 17 Jul 2014 12:46:00 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id s6HGjZhl000318; Thu, 17 Jul 2014 11:45:35 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6HGjZMf005695; Thu, 17 Jul 2014 11:45:35 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Thu, 17 Jul 2014 11:45:35 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s6HGjZIL023848; Thu, 17 Jul 2014 11:45:35 -0500 Received: from localhost (j-172-22-151-213.vpn.ti.com [172.22.151.213]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id s6HGjZt19601; Thu, 17 Jul 2014 11:45:35 -0500 (CDT) From: Dan Murphy To: , , CC: , Dan Murphy Subject: [v3 PATCH 4/6] ARM: dts: am4372: Add prcm_resets node Date: Thu, 17 Jul 2014 11:45:29 -0500 Message-ID: <1405615531-15649-4-git-send-email-dmurphy@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1405615531-15649-1-git-send-email-dmurphy@ti.com> References: <1405615531-15649-1-git-send-email-dmurphy@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the prcm_resets node to the prcm parent node. Add the am34xx_resets file to define the am34xx reset lines that are handled by this reset framework. Signed-off-by: Dan Murphy --- v3 - No changes arch/arm/boot/dts/am4372.dtsi | 7 +++++ arch/arm/boot/dts/am43xx-resets.dtsi | 52 ++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) create mode 100644 arch/arm/boot/dts/am43xx-resets.dtsi diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 49fa596..d0aa9c9 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -88,6 +88,12 @@ prcm_clockdomains: clockdomains { }; + + prcm_resets: resets { + #address-cells = <1>; + #size-cells = <1>; + #reset-cells = <1>; + }; }; scrm: scrm@44e10000 { @@ -892,3 +898,4 @@ }; /include/ "am43xx-clocks.dtsi" +/include/ "am43xx-resets.dtsi" diff --git a/arch/arm/boot/dts/am43xx-resets.dtsi b/arch/arm/boot/dts/am43xx-resets.dtsi new file mode 100644 index 0000000..ef338ba --- /dev/null +++ b/arch/arm/boot/dts/am43xx-resets.dtsi @@ -0,0 +1,52 @@ +/* + * Device Tree Source for AM43XX reset data + * + * Copyright (C) 2014 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&prcm_resets { + icss_rstctrl { + reg = <0x810>, + <0x814>; + + icss_reset: icss_reset { + control-bit = <0x01>; + status-bit = <0x01>; + }; + }; + + gfx_rstctrl { + reg = <0x410>, + <0x414>; + + gfx_reset: gfx_reset { + control-bit = <0x01>; + status-bit = <0x01>; + }; + }; + + per_rstctrl { + reg = <0x2010>, + <0x2014>; + + iva_reset: iva_reset { + control-bit = <0x01>; + status-bit = <0x01>; + }; + }; + + device_rstctrl { + reg = <0x4000>, + <0x4004>; + + device_reset: device_reset { + control-bit = <0x01>; + status-bit = <0x01>; + }; + }; + +};