From patchwork Fri Aug 22 14:01:01 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 4764531 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E756BC0338 for ; Fri, 22 Aug 2014 14:01:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D00E52018E for ; Fri, 22 Aug 2014 14:01:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A62A320172 for ; Fri, 22 Aug 2014 14:01:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932346AbaHVOBb (ORCPT ); Fri, 22 Aug 2014 10:01:31 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:33921 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932170AbaHVOB3 (ORCPT ); Fri, 22 Aug 2014 10:01:29 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id s7ME16rW001933; Fri, 22 Aug 2014 09:01:06 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s7ME14jZ015773; Fri, 22 Aug 2014 09:01:05 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Fri, 22 Aug 2014 09:01:04 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s7ME14DN024484; Fri, 22 Aug 2014 09:01:04 -0500 From: Nishanth Menon To: Linus Walleij , Tony Lindgren , Tero Kristo , Paul Walmsley CC: Kevin Hilman , , , , Keerthy , =?UTF-8?q?Beno=C3=AEt=20Cousson?= , Santosh Shilimkar , , Dave Gerlach , Nishanth Menon Subject: [PATCH 2/3] pinctrl: single: Add DRA7 pinctrl compatibility Date: Fri, 22 Aug 2014 09:01:01 -0500 Message-ID: <1408716062-26055-3-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1408716062-26055-1-git-send-email-nm@ti.com> References: <1408716062-26055-1-git-send-email-nm@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP DRA7 pinctrl definitions now differ from traditional 16 bit OMAP pin ctrl definitions, in that all 32 bits are used to describe a single pin Also the location of wakeupenable and event bits have changed. Signed-off-by: Nishanth Menon Acked-by: Tony Lindgren --- .../bindings/pinctrl/ti,omap-pinctrl.txt | 1 + drivers/pinctrl/pinctrl-single.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt index 156d964..d45386d 100644 --- a/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt @@ -5,5 +5,6 @@ Required properties: "ti,omap3-padconf" - OMAP3 compatible pinctrl "ti,omap4-padconf" - OMAP4 compatible pinctrl "ti,omap5-padconf" - OMAP5 compatible pinctrl + "ti,dra7-padconf" - DRA7 compatible pinctrl See Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt for further details. diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 95dd9cf..598d600 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1981,6 +1981,12 @@ static const struct pcs_soc_data pinctrl_single_omap_wkup = { .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */ }; +static const struct pcs_soc_data pinctrl_single_dra7 = { + .flags = PCS_QUIRK_SHARED_IRQ, + .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */ + .irq_status_mask = (1 << 25), /* WAKEUPEVENT */ +}; + static const struct pcs_soc_data pinctrl_single = { }; @@ -1992,6 +1998,7 @@ static struct of_device_id pcs_of_match[] = { { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup }, { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup }, { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup }, + { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 }, { .compatible = "pinctrl-single", .data = &pinctrl_single }, { .compatible = "pinconf-single", .data = &pinconf_single }, { },