From patchwork Wed Oct 29 09:22:59 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 5185671 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8866FC11AC for ; Wed, 29 Oct 2014 09:25:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B12FA201EF for ; Wed, 29 Oct 2014 09:25:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BA3A8200DF for ; Wed, 29 Oct 2014 09:25:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756545AbaJ2JYw (ORCPT ); Wed, 29 Oct 2014 05:24:52 -0400 Received: from mailout2.w1.samsung.com ([210.118.77.12]:26453 "EHLO mailout2.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756372AbaJ2JXR (ORCPT ); Wed, 29 Oct 2014 05:23:17 -0400 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout2.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NE700A708VCB560@mailout2.w1.samsung.com>; Wed, 29 Oct 2014 09:26:00 +0000 (GMT) X-AuditID: cbfec7f4-b7f6c6d00000120b-e8-5450b20092b3 Received: from eusync1.samsung.com ( [203.254.199.211]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id DA.04.04619.002B0545; Wed, 29 Oct 2014 09:23:12 +0000 (GMT) Received: from amdc1339.digital.local ([106.116.147.30]) by eusync1.samsung.com (Oracle Communications Messaging Server 7u4-23.01 (7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0NE700DWE8QECT50@eusync1.samsung.com>; Wed, 29 Oct 2014 09:23:12 +0000 (GMT) From: Marek Szyprowski To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Tomasz Figa , Kyungmin Park , Russell King - ARM Linux , Kukjin Kim , lauraa@codeaurora.org, linux-omap@vger.kernel.org, linus.walleij@linaro.org, tony@atomide.com, drake@endlessm.com, loeliger@gmail.com, Mark Rutland Subject: [PATCH v7 6/8] ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310 Date: Wed, 29 Oct 2014 10:22:59 +0100 Message-id: <1414574581-2320-7-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.2 In-reply-to: <1414574581-2320-1-git-send-email-m.szyprowski@samsung.com> References: <1414574581-2320-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrMLMWRmVeSWpSXmKPExsVy+t/xy7oMmwJCDLYcEbd4NP8xs0Xvgqts Fmeb3rBbbO+cwW4x5c9yJotNj6+xWlzeNYfNYvaSfhaLGef3MVncvsxrcW77FhaLtUfuslss vX6RyWLVrj+MFvuveDnwe6yZt4bRo6W5h83j29dJLB6X+3qZPBZ9z/LYOesuu8eda3vYPDYv qffo27KK0ePzJrkArigum5TUnMyy1CJ9uwSujOZ3k5gKtopVXLr6gqWBcZtQFyMHh4SAiUTD xqouRk4gU0ziwr31bF2MXBxCAksZJbZevs8C4fQxSSz8eJAVpIpNwFCi620XG4gtIpAt8ePb ZLAiZoE+Zonz03uYQRLCAmESm9b3gTWwCKhKfO/Zyw5i8wq4S+z//5cFYp2cxP+XK5hAbE4B D4nVF5aADRUCqtl4uJttAiPvAkaGVYyiqaXJBcVJ6bmGesWJucWleel6yfm5mxghAf1lB+Pi Y1aHGAU4GJV4eDV2+4cIsSaWFVfmHmKU4GBWEuHdYR4QIsSbklhZlVqUH19UmpNafIiRiYNT qoFRYNKzh04PJ374cKf9io+j5O3JU9jT/BSeswo5nPhgeXZq8M9Sd8E658piBakPMpt6MmLE FVZu1lDkXyrfwP7tdmpiIeu5301cVV5yk/X/FqeenGSzwvUJw5+ZrH94/nf1NDHVzNPe2SK5 8EqQts6GU17rLDWanggVhPoz+NbusGGd2efbWKDEUpyRaKjFXFScCABWqQopRgIAAA== Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Tomasz Figa Exynos4 SoCs equipped with an L2C-310 cache controller and running under secure firmware require certain registers of aforementioned IP to be accessed only from secure mode. This means that SMC calls are required for certain register writes. To handle this, an implementation of .write_sec and .configure callbacks is provided by this patch. Signed-off-by: Tomasz Figa [added comment and reworked unconditional call to SMC_CMD_L2X0INVALL] Signed-off-by: Marek Szyprowski --- arch/arm/mach-exynos/firmware.c | 50 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index f5e626d55951..e6a052c593f2 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -120,6 +121,43 @@ static const struct firmware_ops exynos_firmware_ops = { .resume = exynos_resume, }; +static void exynos_l2_write_sec(unsigned long val, unsigned reg) +{ + static int l2cache_enabled; + + switch (reg) { + case L2X0_CTRL: + if (val & L2X0_CTRL_EN) { + /* + * Before the cache can be enabled, due to firmware + * design, SMC_CMD_L2X0INVALL must be called. + */ + if (!l2cache_enabled) { + exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0); + l2cache_enabled = 1; + } + } else { + l2cache_enabled = 0; + } + exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0); + break; + + case L2X0_DEBUG_CTRL: + exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0); + break; + + default: + WARN_ONCE(1, "%s: ignoring write to reg 0x%x\n", __func__, reg); + } +} + +static void exynos_l2_configure(const struct l2x0_regs *regs) +{ + exynos_smc(SMC_CMD_L2X0SETUP1, regs->tag_latency, regs->data_latency, + regs->prefetch_ctrl); + exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0); +} + void __init exynos_firmware_init(void) { struct device_node *nd; @@ -139,4 +177,16 @@ void __init exynos_firmware_init(void) pr_info("Running under secure firmware.\n"); register_firmware_ops(&exynos_firmware_ops); + + /* + * Exynos 4 SoCs (based on Cortex A9 and equipped with L2C-310), + * running under secure firmware, require certain registers of L2 + * cache controller to be written in secure mode. Here .write_sec + * callback is provided to perform necessary SMC calls. + */ + if (IS_ENABLED(CONFIG_CACHE_L2X0) + && read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) { + outer_cache.write_sec = exynos_l2_write_sec; + outer_cache.configure = exynos_l2_configure; + } }