From patchwork Tue Nov 25 13:11:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: George Cherian X-Patchwork-Id: 5379051 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C8DF1C11AD for ; Tue, 25 Nov 2014 13:20:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5223B201BB for ; Tue, 25 Nov 2014 13:20:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 29D8220108 for ; Tue, 25 Nov 2014 13:20:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753302AbaKYNPz (ORCPT ); Tue, 25 Nov 2014 08:15:55 -0500 Received: from devils.ext.ti.com ([198.47.26.153]:54401 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753164AbaKYNPx (ORCPT ); Tue, 25 Nov 2014 08:15:53 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id sAPDEgqC015151; Tue, 25 Nov 2014 07:14:42 -0600 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id sAPDEgIO031002; Tue, 25 Nov 2014 07:14:42 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.174.1; Tue, 25 Nov 2014 07:14:42 -0600 Received: from george-pc.apr.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id sAPDEBDv020093; Tue, 25 Nov 2014 07:14:36 -0600 From: George Cherian To: , , , , CC: , , , , , , , , , , , , , , , George Cherian Subject: [PATCH 04/19] usb: host xhci: Add XHCI_NEEDS_LHC_RESET quirk Date: Tue, 25 Nov 2014 18:41:40 +0530 Message-ID: <1416921115-10467-5-git-send-email-george.cherian@ti.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1416921115-10467-1-git-send-email-george.cherian@ti.com> References: <1416921115-10467-1-git-send-email-george.cherian@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds XHCI_NEEDS_LHC_RESET quirk, to make sure only Light Host Reset is done during xhci_reset(). This is mainly useful when we switch roles HOST to Device mode and viceversa. The DWC3 IP shares internal RAM for both HOST and Device specific registers. So while switching roles between HOST and Device modes, it's advbised to do a LIGHT HC reset else the already configured global registers of the DWC3 IP gets re-initialized. Signed-off-by: George Cherian --- drivers/usb/host/xhci.c | 5 +++-- drivers/usb/host/xhci.h | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index d4196f8..5dabf9a 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -170,11 +170,12 @@ int xhci_reset(struct xhci_hcd *xhci) xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC"); command = readl(&xhci->op_regs->command); - command |= CMD_RESET; + command |= (xhci->quirks & XHCI_NEEDS_LHC_RESET) ? CMD_LRESET : CMD_RESET; writel(command, &xhci->op_regs->command); ret = xhci_handshake(xhci, &xhci->op_regs->command, - CMD_RESET, 0, 10 * 1000 * 1000); + (xhci->quirks & XHCI_NEEDS_LHC_RESET) ? CMD_LRESET : CMD_RESET, + 0, 10 * 1000 * 1000); if (ret) return ret; diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index 2248058..1b14b09 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1561,6 +1561,7 @@ struct xhci_hcd { /* For controllers with a broken beyond repair streams implementation */ #define XHCI_BROKEN_STREAMS (1 << 19) #define XHCI_DRD_SUPPORT (1 << 20) +#define XHCI_NEEDS_LHC_RESET (1 << 21) unsigned int num_active_eps; unsigned int limit_active_eps; /* There are two roothubs to keep track of bus suspend info for */