From patchwork Fri Jan 2 17:17:51 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 5560131 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1D46CBF6C3 for ; Fri, 2 Jan 2015 17:19:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D35C52025A for ; Fri, 2 Jan 2015 17:19:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BF40320109 for ; Fri, 2 Jan 2015 17:19:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752441AbbABRSz (ORCPT ); Fri, 2 Jan 2015 12:18:55 -0500 Received: from devils.ext.ti.com ([198.47.26.153]:39502 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752331AbbABRSe (ORCPT ); Fri, 2 Jan 2015 12:18:34 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id t02HHuoq006461; Fri, 2 Jan 2015 11:17:56 -0600 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id t02HHuMJ011898; Fri, 2 Jan 2015 11:17:56 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.174.1; Fri, 2 Jan 2015 11:17:55 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id t02HHtOH023627; Fri, 2 Jan 2015 11:17:55 -0600 From: Nishanth Menon To: Tony Lindgren , Russell King CC: , , , Marek Szyprowski , Tomasz Figa , Santosh , Sekhar Nori , Nishanth Menon Subject: [PATCH 1/2] ARM: l2c: OMAP4/AM437x: Introduce support for cache latency programming Date: Fri, 2 Jan 2015 11:17:51 -0600 Message-ID: <1420219072-6521-2-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1420219072-6521-1-git-send-email-nm@ti.com> References: <1420219072-6521-1-git-send-email-nm@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP OMAP4 and AM437x generations of processors support programming the PL310 L2Cache controller's Latency control registers using a secure montior call. Unfortunately, this varies from other PL310 programming sequence with a requirement of two parameters instead of the generic single parameter configuration. Information based on: OMAP4430 Public ROM Code API Functional Specfication revision 0.6 (Oct 27, 2010) OMAP4440 Public ROM Code API Functional Specfication revision 0.1 (Oct 27, 2010) Aegis ROM Code Memory and Peripheral Booting Functional Specification version 1.00 (Jan 1, 2014) Signed-off-by: Nishanth Menon --- arch/arm/mach-omap2/common.h | 1 + arch/arm/mach-omap2/omap-secure.h | 1 + arch/arm/mach-omap2/omap-smc.S | 20 ++++++++++++++++++++ arch/arm/mach-omap2/omap4-common.c | 15 +++++++++++++++ 4 files changed, 37 insertions(+) diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index 19c9144..d5f8a9c 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -240,6 +240,7 @@ extern void gic_dist_enable(void); extern bool gic_dist_disabled(void); extern void gic_timer_retrigger(void); extern void omap_smc1(u32 fn, u32 arg); +extern void omap_smc1_2(u32 fn, u32 arg1, u32 arg2); extern void __iomem *omap4_get_sar_ram_base(void); extern void omap_do_wfi(void); diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index dec2b05..338fdab 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h @@ -42,6 +42,7 @@ #define OMAP4_MON_L2X0_DBG_CTRL_INDEX 0x100 #define OMAP4_MON_L2X0_CTRL_INDEX 0x102 #define OMAP4_MON_L2X0_AUXCTRL_INDEX 0x109 +#define OMAP4_MON_L2X0_SETLATENCY_INDEX 0x112 #define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113 #define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109 diff --git a/arch/arm/mach-omap2/omap-smc.S b/arch/arm/mach-omap2/omap-smc.S index fd90125..caf2bd1 100644 --- a/arch/arm/mach-omap2/omap-smc.S +++ b/arch/arm/mach-omap2/omap-smc.S @@ -33,6 +33,26 @@ ENTRY(omap_smc1) ldmfd sp!, {r2-r12, pc} ENDPROC(omap_smc1) +/* + * This is common routine to manage secure monitor API + * used to modify the PL310 secure registers. + * 'r0' and 'r1' contains the value to be modified and 'r12' contains + * the monitor API number. It uses few CPU registers + * internally and hence they need be backed up including + * link register "lr". + * Function signature : void omap_smc1_2(u32 fn, u32 arg1, u32 arg2) + */ + +ENTRY(omap_smc1_2) + stmfd sp!, {r2-r12, lr} + mov r12, r0 + mov r0, r1 + mov r1, r2 + dsb + smc #0 + ldmfd sp!, {r2-r12, pc} +ENDPROC(omap_smc1_2) + /** * u32 omap_smc2(u32 id, u32 falg, u32 pargs) * Low level common routine for secure HAL and PPA APIs. diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index fe99cef..25a0b2f 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -191,6 +191,21 @@ void omap4_l2c310_write_sec(unsigned long val, unsigned reg) pr_info_once("OMAP L2C310: ROM does not support power control setting\n"); return; + case L310_TAG_LATENCY_CTRL: + case L310_DATA_LATENCY_CTRL: + { + void __iomem *base = omap4_get_l2cache_base(); + u32 data_latency, tag_latency; + + tag_latency = (reg == L310_TAG_LATENCY_CTRL) ? val : + readl_relaxed(base + L310_TAG_LATENCY_CTRL); + data_latency = (reg == L310_DATA_LATENCY_CTRL) ? val : + readl_relaxed(base + L310_DATA_LATENCY_CTRL); + omap_smc1_2(OMAP4_MON_L2X0_SETLATENCY_INDEX, tag_latency, + data_latency); + return; + } + default: WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg); return;