From patchwork Fri Jan 2 17:43:48 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 5560211 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A56EEBF6C3 for ; Fri, 2 Jan 2015 17:44:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C0CCD2021B for ; Fri, 2 Jan 2015 17:44:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6062C201FB for ; Fri, 2 Jan 2015 17:44:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752224AbbABRo2 (ORCPT ); Fri, 2 Jan 2015 12:44:28 -0500 Received: from comal.ext.ti.com ([198.47.26.152]:39026 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750745AbbABRo1 (ORCPT ); Fri, 2 Jan 2015 12:44:27 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id t02HhoLV024799; Fri, 2 Jan 2015 11:43:50 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id t02HhnWW016352; Fri, 2 Jan 2015 11:43:49 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Fri, 2 Jan 2015 11:43:49 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id t02HhnId002329; Fri, 2 Jan 2015 11:43:49 -0600 From: Nishanth Menon To: Tony Lindgren , Russell King CC: , , , Marek Szyprowski , Tomasz Figa , Santosh , Sekhar Nori , Nishanth Menon Subject: [PATCH V2 2/2] ARM: l2c: AM437x: Introduce support for cache filter programming Date: Fri, 2 Jan 2015 11:43:48 -0600 Message-ID: <1420220628-23742-3-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1420220628-23742-1-git-send-email-nm@ti.com> References: <1420220628-23742-1-git-send-email-nm@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP AM437x generation of processors support programming the PL310 L2Cache controller's address filter start and end registers using a secure montior service. Unfortunately, this secure monitor service is not supported on OMAP4 generation of processors. Information based on: OMAP4430 Public ROM Code API Functional Specfication revision 0.6 (Oct 27, 2010) OMAP4440 Public ROM Code API Functional Specfication revision 0.1 (Oct 27, 2010) Aegis ROM Code Memory and Peripheral Booting Functional Specification version 1.00 (Jan 21, 2014) Signed-off-by: Nishanth Menon --- Changes in V2: - smc call should use filter start in r0 and filter end in r1. - Document version update. V1: https://patchwork.kernel.org/patch/5560111/ arch/arm/mach-omap2/omap-secure.h | 1 + arch/arm/mach-omap2/omap4-common.c | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index 338fdab..569e167 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h @@ -44,6 +44,7 @@ #define OMAP4_MON_L2X0_AUXCTRL_INDEX 0x109 #define OMAP4_MON_L2X0_SETLATENCY_INDEX 0x112 #define OMAP4_MON_L2X0_PREFETCH_INDEX 0x113 +#define AM43X_MON_L2X0_SETFILTER_INDEX 0x114 #define OMAP5_DRA7_MON_SET_CNTFRQ_INDEX 0x109 #define OMAP5_MON_AMBA_IF_INDEX 0x108 diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 25a0b2f..0b1454d 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -206,6 +206,27 @@ void omap4_l2c310_write_sec(unsigned long val, unsigned reg) return; } + case L310_ADDR_FILTER_START: + case L310_ADDR_FILTER_END: + { + void __iomem *base; + u32 filter_start, filter_end; + + if (!soc_is_am437x()) { + pr_info_once("OMAP L2C310: ROM does not support filter setting\n"); + return; + } + + base = omap4_get_l2cache_base(); + filter_start = (reg == L310_ADDR_FILTER_START) ? val : + readl_relaxed(base + L310_ADDR_FILTER_START); + filter_end = (reg == L310_ADDR_FILTER_END) ? val : + readl_relaxed(base + L310_ADDR_FILTER_END); + omap_smc1_2(AM43X_MON_L2X0_SETFILTER_INDEX, filter_start, + filter_end); + return; + } + default: WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg); return;