From patchwork Wed Jan 7 17:42:40 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 5586441 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 42F229F357 for ; Wed, 7 Jan 2015 17:43:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7242220254 for ; Wed, 7 Jan 2015 17:43:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9040C202AE for ; Wed, 7 Jan 2015 17:43:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754227AbbAGRnV (ORCPT ); Wed, 7 Jan 2015 12:43:21 -0500 Received: from foss-mx-na.foss.arm.com ([217.140.108.86]:57009 "EHLO foss-mx-na.foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754043AbbAGRnU (ORCPT ); Wed, 7 Jan 2015 12:43:20 -0500 Received: from foss-smtp-na-1.foss.arm.com (unknown [10.80.61.8]) by foss-mx-na.foss.arm.com (Postfix) with ESMTP id 497894E5; Wed, 7 Jan 2015 11:43:16 -0600 (CST) Received: from collaborate-mta1.arm.com (highbank-bc01-b06.austin.arm.com [10.112.81.134]) by foss-smtp-na-1.foss.arm.com (Postfix) with ESMTP id F1A555FAD7; Wed, 7 Jan 2015 11:43:13 -0600 (CST) Received: from approximate.cambridge.arm.com (approximate.cambridge.arm.com [10.1.209.148]) by collaborate-mta1.arm.com (Postfix) with ESMTP id 4D1FA13F78C; Wed, 7 Jan 2015 11:43:11 -0600 (CST) From: Marc Zyngier To: Stephen Warren , Thierry Reding , Alexandre Courbot , Benoit Cousson , Tony Lindgren , Nishanth Menon , Santosh Shilimkar , Shawn Guo , Sascha Hauer , Kukjin Kim , Simon Horman , Magnus Damm , Linus Walleij , Michal Simek , Rob Herring , Mark Rutland , Jason Cooper , Thomas Gleixner Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-omap@vger.kernel.org Subject: [PATCH v2 05/21] DT: tegra: add binding for the legacy interrupt controller Date: Wed, 7 Jan 2015 17:42:40 +0000 Message-Id: <1420652576-22309-6-git-send-email-marc.zyngier@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1420652576-22309-1-git-send-email-marc.zyngier@arm.com> References: <1420652576-22309-1-git-send-email-marc.zyngier@arm.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Marc Zyngier --- .../interrupt-controller/nvidia,tegra-ictlr.txt | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt new file mode 100644 index 0000000..44fd873 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt @@ -0,0 +1,39 @@ +NVIDIA Legacy Interrupt Controller + +All Tegra SoCs contain a legacy interrupt controller that routes +interrupts to the GIC, and also serves as a wakeup source. It is also +refered to as "ictlr", hence the name of the binding. + +The HW block exposes a number of frames, each implementing a set of 32 +interrupts. + +Reguired properties: + +- compatible : should contain at least "nvidia,tegra-ictlr". +- reg : Specifies base physical address and size of the registers. + Each frame must be described separately. +- interrupt-controller : Identifies the node as an interrupt controller. +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value must be 3. +- interrupt-parent : a phandle to the GIC these interrupts are routed + to. + +Notes: + +- Because this HW ultimately routes interrupts to the GIC, the + interrupt specifier must be that of the GIC. +- Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs + are explicitely forbiden. + +Example: + + ictlr: interrupt-controller@60004000 { + compatible = "nvidia,tegra20-ictlr", "nvidia,tegra-ictlr"; + reg = <0x60004000 64>, + <0x60004100 64>, + <0x60004200 64>, + <0x60004300 64>; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + };