From patchwork Mon Jan 12 18:26:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 5613391 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 934AF9F358 for ; Mon, 12 Jan 2015 18:27:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D191920558 for ; Mon, 12 Jan 2015 18:27:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0BAB120591 for ; Mon, 12 Jan 2015 18:27:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751355AbbALS1j (ORCPT ); Mon, 12 Jan 2015 13:27:39 -0500 Received: from foss-mx-na.foss.arm.com ([217.140.108.86]:60551 "EHLO foss-mx-na.foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752617AbbALS1c (ORCPT ); Mon, 12 Jan 2015 13:27:32 -0500 Received: from foss-smtp-na-1.foss.arm.com (unknown [10.80.61.8]) by foss-mx-na.foss.arm.com (Postfix) with ESMTP id 091BB2C0; Mon, 12 Jan 2015 12:27:24 -0600 (CST) Received: from collaborate-mta1.arm.com (highbank-bc01-b06.austin.arm.com [10.112.81.134]) by foss-smtp-na-1.foss.arm.com (Postfix) with ESMTP id AD8255FAD7; Mon, 12 Jan 2015 12:27:21 -0600 (CST) Received: from approximate.cambridge.arm.com (approximate.cambridge.arm.com [10.1.209.148]) by collaborate-mta1.arm.com (Postfix) with ESMTP id BEB8013F8D8; Mon, 12 Jan 2015 12:27:18 -0600 (CST) From: Marc Zyngier To: Stephen Warren , Thierry Reding , Alexandre Courbot , Benoit Cousson , Tony Lindgren , Nishanth Menon , Santosh Shilimkar , Shawn Guo , Sascha Hauer , Kukjin Kim , Simon Horman , Magnus Damm , Linus Walleij , Michal Simek , Rob Herring , Mark Rutland , Jason Cooper , Thomas Gleixner Cc: Stefan Agner , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-omap@vger.kernel.org Subject: [PATCH v3 17/21] irqchip: gic: add an entry point to set up irqchip flags Date: Mon, 12 Jan 2015 18:26:23 +0000 Message-Id: <1421087187-26988-18-git-send-email-marc.zyngier@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1421087187-26988-1-git-send-email-marc.zyngier@arm.com> References: <1421087187-26988-1-git-send-email-marc.zyngier@arm.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP A common use of gic_arch_extn is to set up additional flags to the GIC irqchip. It looks like a benign enough hack that doesn't really require the users of that feature to be converted to stacked domains. Add a gic_set_irqchip_flags() function that platform code can call instead of using the dreaded gic_arch_extn. Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-gic.c | 5 +++++ include/linux/irqchip/arm-gic.h | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 9c30a76..23fe3be 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -877,6 +877,11 @@ static const struct irq_domain_ops gic_irq_domain_ops = { .xlate = gic_irq_domain_xlate, }; +void gic_set_irqchip_flags(unsigned long flags) +{ + gic_chip.flags |= flags; +} + void __init gic_init_bases(unsigned int gic_nr, int irq_start, void __iomem *dist_base, void __iomem *cpu_base, u32 percpu_offset, struct device_node *node) diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h index 3978c5b..36ec4ae 100644 --- a/include/linux/irqchip/arm-gic.h +++ b/include/linux/irqchip/arm-gic.h @@ -97,6 +97,7 @@ struct device_node; extern struct irq_chip gic_arch_extn; +void gic_set_irqchip_flags(unsigned long flags); void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *, u32 offset, struct device_node *); void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);