From patchwork Fri Mar 13 22:58:37 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 6010131 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 9B5D99F318 for ; Fri, 13 Mar 2015 23:00:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C09B320225 for ; Fri, 13 Mar 2015 23:00:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C392620266 for ; Fri, 13 Mar 2015 23:00:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756991AbbCMW6s (ORCPT ); Fri, 13 Mar 2015 18:58:48 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:46919 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756812AbbCMW6p (ORCPT ); Fri, 13 Mar 2015 18:58:45 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id t2DMwf6s030703; Fri, 13 Mar 2015 17:58:41 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id t2DMwe2H017427; Fri, 13 Mar 2015 17:58:40 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.224.2; Fri, 13 Mar 2015 17:58:39 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id t2DMwdrU031056; Fri, 13 Mar 2015 17:58:39 -0500 Received: from localhost (irmo.am.dhcp.ti.com [128.247.71.175]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id t2DMwd903949; Fri, 13 Mar 2015 17:58:39 -0500 (CDT) From: Suman Anna To: Tero Kristo CC: Mike Turquette , Stephen Boyd , , , Suman Anna Subject: [PATCH 3/4] CLK: TI: DRA7: Correct timer_sys_ck clock aliases for Timers Date: Fri, 13 Mar 2015 17:58:37 -0500 Message-ID: <1426287518-47786-4-git-send-email-s-anna@ti.com> X-Mailer: git-send-email 2.3.2 In-Reply-To: <1426287518-47786-1-git-send-email-s-anna@ti.com> References: <1426287518-47786-1-git-send-email-s-anna@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The OMAP DMTimer API, omap_dm_timer_set_source(), can set the parent of a timer node using 3 different values that use fixed parent names for the clocks. The parent name, timer_sys_ck, is used for setting the parent when used with the source index OMAP_TIMER_SRC_SYS_CLK. This should point to the TIMER_SYS_CLK and not the SYSCLKIN2, so correct the clock aliases appropriately. SYSCLKIN2 is not a mandatory clock input. Signed-off-by: Suman Anna --- drivers/clk/ti/clk-7xx.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index ee32f4deebf4..256295eb5157 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c @@ -289,13 +289,13 @@ static struct ti_dt_clk dra7xx_clks[] = { DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"), DT_CLK("omap_wdt", "ick", "dummy_ck"), DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), - DT_CLK("4ae18000.timer", "timer_sys_ck", "sys_clkin2"), - DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin2"), - DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin2"), - DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin2"), - DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin2"), - DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin2"), - DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin2"), + DT_CLK("4ae18000.timer", "timer_sys_ck", "timer_sys_clk_div"), + DT_CLK("48032000.timer", "timer_sys_ck", "timer_sys_clk_div"), + DT_CLK("48034000.timer", "timer_sys_ck", "timer_sys_clk_div"), + DT_CLK("48036000.timer", "timer_sys_ck", "timer_sys_clk_div"), + DT_CLK("4803e000.timer", "timer_sys_ck", "timer_sys_clk_div"), + DT_CLK("48086000.timer", "timer_sys_ck", "timer_sys_clk_div"), + DT_CLK("48088000.timer", "timer_sys_ck", "timer_sys_clk_div"), DT_CLK("48820000.timer", "timer_sys_ck", "timer_sys_clk_div"), DT_CLK("48822000.timer", "timer_sys_ck", "timer_sys_clk_div"), DT_CLK("48824000.timer", "timer_sys_ck", "timer_sys_clk_div"),