From patchwork Mon Mar 23 12:18:25 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Grygorii.Strashko@linaro.org" X-Patchwork-Id: 6071831 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 93427BF90F for ; Mon, 23 Mar 2015 12:20:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id EE8CD2025B for ; Mon, 23 Mar 2015 12:20:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E4BB7201F4 for ; Mon, 23 Mar 2015 12:20:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752677AbbCWMUU (ORCPT ); Mon, 23 Mar 2015 08:20:20 -0400 Received: from mail-la0-f43.google.com ([209.85.215.43]:33672 "EHLO mail-la0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752331AbbCWMSj (ORCPT ); Mon, 23 Mar 2015 08:18:39 -0400 Received: by labto5 with SMTP id to5so24740753lab.0 for ; Mon, 23 Mar 2015 05:18:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KlMT9+knBmdCC42n5TQDDZObFbnXXY2KrRQkn41ho/w=; b=K23RzkpouZzNxN3+sfU2K9i7deRhGC8hkMebnyief07Th643qRYY0PS/07P1E3CIIr xIa5kpsohFkWjZ93cjr68zmxFUGKwW9g1H820sjuCwVlWWsYSIeG8kBi+qM/EyZlCtyu 3fkOxtG+GyFJJiQ7D2FNzaNW3Ot+i+exgtGOSEgnNiKb44S/S8UJ14Os+WtX1xad0P1p UqVcyvaSZtm00ViVsbX1FOBeFQTG+tXugeDvHI4uc+IugkU9DthXfvph/+NkI44E6Cso jWvZD9lvNvI0K1ZCwgrQlDoy6VeNtZpJIkuxIrkltu3q7Y+s9lVSJ5+NHP2XsTVe9Ks/ G8zg== X-Gm-Message-State: ALoCoQmhpmyA0Rkyw1997ocKBASJAi+btzbRH09z24yG5+x3EnIuXzDuCA1eXeOUV/OqN248sO9k X-Received: by 10.152.43.229 with SMTP id z5mr76090713lal.48.1427113117641; Mon, 23 Mar 2015 05:18:37 -0700 (PDT) Received: from localhost ([195.238.92.128]) by mx.google.com with ESMTPSA id az19sm140287lab.45.2015.03.23.05.18.37 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 23 Mar 2015 05:18:37 -0700 (PDT) From: To: Javier Martinez Canillas , Linus Walleij , Alexandre Courbot , ssantosh@kernel.org, Kevin Hilman , tony@atomide.com Cc: linux-omap@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Grygorii Strashko Subject: [PATCH v2 3/8] gpio: omap: convert debounce functions switch to use gpio offset Date: Mon, 23 Mar 2015 14:18:25 +0200 Message-Id: <1427113110-20813-4-git-send-email-grygorii.strashko@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1427113110-20813-1-git-send-email-grygorii.strashko@linaro.org> References: <1427113110-20813-1-git-send-email-grygorii.strashko@linaro.org> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Grygorii Strashko Convert debounce functions to use GPIO offset instead of system GPIO numbers. This allows to drop unneeded conversations between system GPIO <-> GPIO offset which are done in many places and many times. It is safe to do now because: - gpiolib always passes GPIO offset to GPIO controller - OMAP GPIO driver converted to use IRQ domain This is preparation step before removing: #define GPIO_INDEX(bank, gpio) #define GPIO_BIT(bank, gpio) int omap_irq_to_gpio() Tested-by: Tony Lindgren Tested-by: Aaro Koskinen Acked-by: Santosh Shilimkar Acked-by: Javier Martinez Canillas Signed-off-by: Grygorii Strashko --- drivers/gpio/gpio-omap.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index 7aeee7b..2df693b 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c @@ -208,13 +208,13 @@ static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) /** * omap2_set_gpio_debounce - low level gpio debounce time * @bank: the gpio bank we're acting upon - * @gpio: the gpio number on this @gpio + * @offset: the gpio number on this @bank * @debounce: debounce time to use * * OMAP's debounce time is in 31us steps so we need * to convert and round up to the closest unit. */ -static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, +static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, unsigned debounce) { void __iomem *reg; @@ -231,7 +231,7 @@ static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, else debounce = (debounce / 0x1f) - 1; - l = GPIO_BIT(bank, gpio); + l = BIT(offset); clk_prepare_enable(bank->dbck); reg = bank->base + bank->regs->debounce; @@ -266,16 +266,16 @@ static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, /** * omap_clear_gpio_debounce - clear debounce settings for a gpio * @bank: the gpio bank we're acting upon - * @gpio: the gpio number on this @gpio + * @offset: the gpio number on this @bank * * If a gpio is using debounce, then clear the debounce enable bit and if * this is the only gpio in this bank using debounce, then clear the debounce * time too. The debounce clock will also be disabled when calling this function * if this is the only gpio in the bank using debounce. */ -static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio) +static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset) { - u32 gpio_bit = GPIO_BIT(bank, gpio); + u32 gpio_bit = BIT(offset); if (!bank->dbck_flag) return; @@ -659,7 +659,7 @@ static void omap_reset_gpio(struct gpio_bank *bank, int gpio) omap_set_gpio_irqenable(bank, gpio, 0); omap_clear_gpio_irqstatus(bank, gpio); omap_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); - omap_clear_gpio_debounce(bank, gpio); + omap_clear_gpio_debounce(bank, GPIO_INDEX(bank, gpio)); } /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */