From patchwork Fri Sep 18 18:16:31 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 7220111 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 76D869F32B for ; Fri, 18 Sep 2015 18:18:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9133B208BC for ; Fri, 18 Sep 2015 18:17:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9BA3C208B4 for ; Fri, 18 Sep 2015 18:17:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752618AbbIRSRf (ORCPT ); Fri, 18 Sep 2015 14:17:35 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:54625 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751760AbbIRSRF (ORCPT ); Fri, 18 Sep 2015 14:17:05 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id t8IIGbHf013543; Fri, 18 Sep 2015 13:16:37 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id t8IIGb5i014221; Fri, 18 Sep 2015 13:16:37 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.224.2; Fri, 18 Sep 2015 13:16:37 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id t8IIGb7F029098; Fri, 18 Sep 2015 13:16:37 -0500 Received: from localhost (irmo.am.dhcp.ti.com [128.247.9.166]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id t8IIGb901951; Fri, 18 Sep 2015 13:16:37 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: , , , Suman Anna Subject: [PATCH 2/5] ARM: dts: DRA72x: Add IPC sub-mailbox nodes for IPU1, IPU2 & DSP1 Date: Fri, 18 Sep 2015 13:16:31 -0500 Message-ID: <1442600194-62520-3-git-send-email-s-anna@ti.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1442600194-62520-1-git-send-email-s-anna@ti.com> References: <1442600194-62520-1-git-send-email-s-anna@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the sub-mailbox nodes that are used to communicate between MPU and the remote processors IPU1, IPU2 and DSP1. These match the respective node definitions on DRA74x to maintain compatibility for the equivalent remote processors. There is no DSP2 on DRA72x, and so the corresponding sub-mailbox node is not added. These sub-mailbox nodes are added to match the hard-coded mailbox configuration used within the TI IPC 3.x software package. The Dual-Cortex M4 IPU1 and IPU2 processor sub-systems are assumed to be running in SMP-mode, and hence only a single sub-mailbox node is added for each. All these sub-mailbox nodes are left in disabled state, and should be enabled (and modified if needed) as per the individual product configuration in the corresponding board dts files. Signed-off-by: Suman Anna --- arch/arm/boot/dts/dra72x.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi index eaca143faa77..70a217050a4c 100644 --- a/arch/arm/boot/dts/dra72x.dtsi +++ b/arch/arm/boot/dts/dra72x.dtsi @@ -45,3 +45,24 @@ <&dss_video1_clk>; clock-names = "fck", "video1_clk"; }; + +&mailbox5 { + mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + ti,mbox-tx = <6 2 2>; + ti,mbox-rx = <4 2 2>; + status = "disabled"; + }; + mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + ti,mbox-tx = <5 2 2>; + ti,mbox-rx = <1 2 2>; + status = "disabled"; + }; +}; + +&mailbox6 { + mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + ti,mbox-tx = <6 2 2>; + ti,mbox-rx = <4 2 2>; + status = "disabled"; + }; +};