From patchwork Tue Mar 8 01:23:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Franklin Cooper X-Patchwork-Id: 8528261 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E7509C0553 for ; Tue, 8 Mar 2016 01:24:44 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DE72220148 for ; Tue, 8 Mar 2016 01:24:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CD790201C0 for ; Tue, 8 Mar 2016 01:24:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753594AbcCHBYh (ORCPT ); Mon, 7 Mar 2016 20:24:37 -0500 Received: from mail-pa0-f65.google.com ([209.85.220.65]:36487 "EHLO mail-pa0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753854AbcCHBYL (ORCPT ); Mon, 7 Mar 2016 20:24:11 -0500 Received: by mail-pa0-f65.google.com with SMTP id 1so72643pal.3; Mon, 07 Mar 2016 17:24:11 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1SRvfI7JP16O/5m9xRqYUP0qDpU/BL4U7pTn6blmdGQ=; b=f4MKAYCABXutIoK+oqe/NULbITZ3kC1thVFfawaqvmUw653FHD0UlNw8rlDwZT7Qz0 8AKrajRxw99PGB6s3pmvQfBN5Z+dkzT99YdNwyNf+XoDM82gV4rJ2i5S1mzfF3icXMcV SlidCn703rNdocy57YOvQ4UIAH+rycJhf4VHA0zEFQDjLsgEPxxvxmixj3xzWKcmR+xO jXmDVpraKVya7haQXeO9umk1m7WIjiMJu78TE6cWClfRKVdUeS0fcezWJ8bL448FmYmm oo9WEx+YS8mchG8g2GWMltlRs2mPYX8IxYoXU+PyZN5rSdESavEsz3AjouT+OX4/y6NV 94jQ== X-Gm-Message-State: AD7BkJIlB0O8cKmsU9s4SdT7QeOtZ3yndVJDOI3tLy3C7GtFVS09IVr+FgnXu93fCDztyw== X-Received: by 10.66.61.204 with SMTP id s12mr38479599par.108.1457400250614; Mon, 07 Mar 2016 17:24:10 -0800 (PST) Received: from beast-server.fios-router.home (pool-173-57-21-86.dllstx.fios.verizon.net. [173.57.21.86]) by smtp.gmail.com with ESMTPSA id 82sm294823pfi.78.2016.03.07.17.24.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Mar 2016 17:24:10 -0800 (PST) From: Franklin S Cooper Jr To: thierry.reding@gmail.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, bcousson@baylibre.com, tony@atomide.com, linux@arm.linux.org.uk, paul@pwsan.com, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, vigneshr@ti.com Cc: Franklin S Cooper Jr Subject: [PATCH v5 6/6] ARM: dts: DRA7: Add dt nodes for PWMSS Date: Mon, 7 Mar 2016 19:23:44 -0600 Message-Id: <1457400224-24797-7-git-send-email-fcooper@ti.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1457400224-24797-1-git-send-email-fcooper@ti.com> References: <1457400224-24797-1-git-send-email-fcooper@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Vignesh R Add PWMSS device tree nodes for DRA7 SoC family and add documentation for dt bindings. Signed-off-by: Vignesh R [fcooper@ti.com: Add eCAP and use updated bindings for PWMSS and ePWM] Signed-off-by: Franklin S Cooper Jr --- Version 5 changes: Add DT node for eCAP and update eCAP binding documentation Version 4 changes: Updated link to the latest documentation .../devicetree/bindings/pwm/pwm-tiecap.txt | 9 +++ .../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 9 +++ .../devicetree/bindings/pwm/pwm-tipwmss.txt | 15 +++- arch/arm/boot/dts/dra7.dtsi | 84 ++++++++++++++++++++++ 4 files changed, 116 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt index 72a8f26..fb9ea89 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt @@ -4,6 +4,7 @@ Required properties: - compatible: Must be "ti,-ecap". for am33xx - compatible = "ti,am33xx-ecap"; for da850 - compatible = "ti,da850-ecap", "ti,am33xx-ecap"; + for dra7xx - compatible = "ti,dra7xx-ecap", "ti,am33xx-ecap"; - #pwm-cells: should be 3. See pwm.txt in this directory for a description of the cells format. The PWM channel index ranges from 0 to 4. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. @@ -26,3 +27,11 @@ ecap0: ecap@0 { /* ECAP on da850 */ #pwm-cells = <3>; reg = <0x306000 0x80>; }; + +ecap0: ecap@4843e100 { + compatible = "ti,dra7xx-ecap", + "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x4843e100 0x80>; +}; + diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt index 345d3f6..5965b9d 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt @@ -4,6 +4,7 @@ Required properties: - compatible: Must be "ti,-ehrpwm". for am33xx - compatible = "ti,am33xx-ehrpwm"; for da850 - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; + for dra7xx - compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm"; - #pwm-cells: should be 3. See pwm.txt in this directory for a description of the cells format. The only third cell flag supported by this binding is PWM_POLARITY_INVERTED. @@ -28,3 +29,11 @@ ehrpwm0: pwm@01f00000 { /* EHRPWM on da850 */ #pwm-cells = <3>; reg = <0x300000 0x2000>; }; + +ehrpwm0: pwm@4843e200 { /* EHRPWM on dra7xx */ + compatible = "ti,dra7xx-ehrpwm", "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48440200 0x80>; + clocks = <&ehrpwm0_tbclk>; + clock-names = "tbclk"; +}; diff --git a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt index 672fa71..f137d0b 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt @@ -1,7 +1,9 @@ TI SOC based PWM Subsystem Required properties: -- compatible: Must be "ti,am33xx-pwmss"; +- compatible: Must be "ti,-pwmss". + for am33xx - compatible = "ti,am33xx-pwmss" + for dra7xx - compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss" - reg: physical base address and size of the registers map. - address-cells: Specify the number of u32 entries needed in child nodes. Should set to 1. @@ -25,3 +27,14 @@ pwmss0: pwmss@48300000 { /* child nodes go here */ }; + +epwmss0: epwmss@4843e000 { /* On DRA7xx */ + compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss"; + reg = <0x4843e000 0x30>; + ti,hwmods = "epwmss0"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* child nodes go here */ +}; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index c4d9175..db62f55 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1597,6 +1597,90 @@ clock-names = "fck", "sys_clk"; }; }; + + epwmss0: epwmss@4843e000 { + compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss"; + reg = <0x4843e000 0x30>; + ti,hwmods = "epwmss0"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges; + + ehrpwm0: pwm@4843e200 { + compatible = "ti,dra7xx-ehrpwm", + "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x4843e200 0x80>; + clocks = <&ehrpwm0_tbclk>; + clock-names = "tbclk"; + status = "disabled"; + }; + + ecap0: ecap@4843e100 { + compatible = "ti,dra7xx-ecap", + "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x4843e100 0x80>; + status = "disabled"; + }; + }; + + epwmss1: epwmss@48440000 { + compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss"; + reg = <0x48440000 0x30>; + ti,hwmods = "epwmss1"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges; + + ehrpwm1: pwm@48440200 { + compatible = "ti,dra7xx-ehrpwm", + "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48440200 0x80>; + clocks = <&ehrpwm1_tbclk>; + clock-names = "tbclk"; + status = "disabled"; + }; + + ecap1: ecap@48440100 { + compatible = "ti,dra7xx-ecap", + "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x48440100 0x80>; + status = "disabled"; + }; + }; + + epwmss2: epwmss@48442000 { + compatible = "ti,dra7xx-pwmss", "ti,am33xx-pwmss"; + reg = <0x48442000 0x30>; + ti,hwmods = "epwmss2"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + ranges; + + ehrpwm2: pwm@48442200 { + compatible = "ti,dra7xx-ehrpwm", + "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48442200 0x80>; + clocks = <&ehrpwm2_tbclk>; + clock-names = "tbclk"; + status = "disabled"; + }; + + ecap2: ecap@48442100 { + compatible = "ti,dra7xx-ecap", + "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x48442100 0x80>; + status = "disabled"; + }; + }; }; thermal_zones: thermal-zones {