From patchwork Thu Mar 17 14:19:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 8611541 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E1B0B9F3D1 for ; Thu, 17 Mar 2016 14:21:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C8C2E20373 for ; Thu, 17 Mar 2016 14:21:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E89F02035E for ; Thu, 17 Mar 2016 14:21:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S967197AbcCQOVV (ORCPT ); Thu, 17 Mar 2016 10:21:21 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:11500 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S967117AbcCQOU3 (ORCPT ); Thu, 17 Mar 2016 10:20:29 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Thu, 17 Mar 2016 07:20:23 -0700 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Thu, 17 Mar 2016 07:19:38 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Thu, 17 Mar 2016 07:19:38 -0700 Received: from jonathanh-lm.nvidia.com (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.406.0; Thu, 17 Mar 2016 07:20:28 -0700 From: Jon Hunter To: Thomas Gleixner , Jason Cooper , Marc Zyngier , =?UTF-8?q?Beno=C3=AEt=20Cousson?= , Tony Lindgren , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Stephen Warren , Thierry Reding CC: Kevin Hilman , Geert Uytterhoeven , Grygorii Strashko , Lars-Peter Clausen , Linus Walleij , linux-tegra@vger.kernel.org, linux-omap@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jon Hunter Subject: [PATCH 14/15] dt-bindings: arm-gic: Drop 'clock-names' from binding document Date: Thu, 17 Mar 2016 14:19:18 +0000 Message-ID: <1458224359-32665-15-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1458224359-32665-1-git-send-email-jonathanh@nvidia.com> References: <1458224359-32665-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Commit afbbd2338176 ("irqchip/gic: Document optional Clock and Power Domain properties") documented optional clock and power-dmoain properties for the ARM GIC. Currently, there are no users of these and for the Tegra210 Audio GIC (based upon the GIC-400) there are two clocks, a functional clock and interface clock, that need to be enabled. To allow flexibility, drop the 'clock-names' from the GIC binding and just provide a list of clocks which the driver can parse. It is assumed that any clocks that are listed, need to be enabled in order to access the GIC. Signed-off-by: Jon Hunter --- Please note that I am not sure if this will be popular, but I am trying to come up with a generic way to handle multiple clocks that may be required for accessing a GIC. .../devicetree/bindings/interrupt-controller/arm,gic.txt | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt index 793c20ff8fcc..c471d1a7a8ea 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt @@ -61,15 +61,8 @@ Optional regions, used when the GIC doesn't have banked registers. The offset is cpu-offset * cpu-nr. -- clocks : List of phandle and clock-specific pairs, one for each entry - in clock-names. -- clock-names : List of names for the GIC clock input(s). Valid clock names - depend on the GIC variant: - "ic_clk" (for "arm,arm11mp-gic") - "PERIPHCLKEN" (for "arm,cortex-a15-gic") - "PERIPHCLK", "PERIPHCLKEN" (for "arm,cortex-a9-gic") - "clk" (for "arm,gic-400") - "gclk" (for "arm,pl390") +- clocks : List of phandle and clock-specific pairs required for + accessing the GIC. - power-domains : A phandle and PM domain specifier as defined by bindings of the power controller specified by phandle, used when the GIC