From patchwork Wed Apr 20 11:03:56 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 8888331 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C83EA9F39A for ; Wed, 20 Apr 2016 11:05:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E4A5F200D4 for ; Wed, 20 Apr 2016 11:05:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 412D82024D for ; Wed, 20 Apr 2016 11:05:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933930AbcDTLFH (ORCPT ); Wed, 20 Apr 2016 07:05:07 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:17568 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754205AbcDTLFD (ORCPT ); Wed, 20 Apr 2016 07:05:03 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Wed, 20 Apr 2016 04:05:00 -0700 Received: from HQMAIL107.nvidia.com ([172.20.187.13]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 20 Apr 2016 04:04:56 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 20 Apr 2016 04:04:56 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Wed, 20 Apr 2016 11:05:02 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Wed, 20 Apr 2016 11:05:01 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Wed, 20 Apr 2016 11:05:01 +0000 Received: from jonathanh-lm.nvidia.com (Not Verified[10.21.132.108]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Wed, 20 Apr 2016 04:05:01 -0700 From: Jon Hunter To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , "Pawel Moll" , Mark Rutland , Ian Campbell , Kumar Gala , "Stephen Warren" , Thierry Reding CC: Kevin Hilman , Geert Uytterhoeven , Grygorii Strashko , Lars-Peter Clausen , Linus Walleij , , , , , Jon Hunter Subject: [PATCH V2 13/14] dt-bindings: arm-gic: Add documentation for Tegra210 AGIC Date: Wed, 20 Apr 2016 12:03:56 +0100 Message-ID: <1461150237-15580-14-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1461150237-15580-1-git-send-email-jonathanh@nvidia.com> References: <1461150237-15580-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Tegra AGIC interrupt controller is compatible with the ARM GIC-400 interrupt controller. The Tegra AGIC requires two clocks, namely the "ape" (functional) and "apb2ape" (interface) clocks, to operate. Add the compatible string and clock information for the AGIC to the GIC device-tree binding documentation. Signed-off-by: Jon Hunter --- I am not sure if it will be popular to add Tegra specific clock names to the GIC DT docs. However, in that case, then possibly the only alternative is to move the Tegra AGIC driver into its own file and expose the GIC APIs for it to use. Then we could add our own DT doc for the Tegra AGIC as well (based upon the ARM GIC). Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt index 793c20ff8fcc..6f34267f1438 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt @@ -21,6 +21,7 @@ Main node required properties: "arm,pl390" "arm,tc11mp-gic" "brcm,brahma-b15-gic" + "nvidia,tegra210-agic" "qcom,msm-8660-qgic" "qcom,msm-qgic2" - interrupt-controller : Identifies the node as an interrupt controller @@ -70,6 +71,7 @@ Optional "PERIPHCLK", "PERIPHCLKEN" (for "arm,cortex-a9-gic") "clk" (for "arm,gic-400") "gclk" (for "arm,pl390") + "ape" and "apb2ape" (for "nvidia,tegra,agic") - power-domains : A phandle and PM domain specifier as defined by bindings of the power controller specified by phandle, used when the GIC