From patchwork Wed May 4 16:25:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 9016501 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2378B9F30C for ; Wed, 4 May 2016 16:26:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 47F5C203C4 for ; Wed, 4 May 2016 16:26:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6D543203B7 for ; Wed, 4 May 2016 16:26:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754298AbcEDQ0n (ORCPT ); Wed, 4 May 2016 12:26:43 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:8418 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754303AbcEDQ0l (ORCPT ); Wed, 4 May 2016 12:26:41 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Wed, 04 May 2016 09:26:44 -0700 Received: from HQMAIL105.nvidia.com ([172.20.187.12]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 04 May 2016 09:26:02 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 04 May 2016 09:26:02 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Wed, 4 May 2016 16:26:40 +0000 Received: from HQMAIL106.nvidia.com (172.18.146.12) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Wed, 4 May 2016 16:26:40 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Wed, 4 May 2016 16:26:39 +0000 Received: from jonathanh-lm.nvidia.com (Not Verified[10.21.132.133]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Wed, 04 May 2016 09:26:39 -0700 From: Jon Hunter To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , "Pawel Moll" , Mark Rutland , Ian Campbell , Kumar Gala , "Stephen Warren" , Thierry Reding CC: Kevin Hilman , Geert Uytterhoeven , Grygorii Strashko , Lars-Peter Clausen , Linus Walleij , , , , , Jon Hunter Subject: [PATCH V3 13/17] irqchip/gic: Don't allow early initialisation if GIC requires RPM Date: Wed, 4 May 2016 17:25:26 +0100 Message-ID: <1462379130-11742-14-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1462379130-11742-1-git-send-email-jonathanh@nvidia.com> References: <1462379130-11742-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Commit afbbd2338176 ("irqchip/gic: Document optional Clock and Power Domain properties") updated the device-tree binding documentation for the GIC to add optional clock and power domain information. Currently, the GIC driver does support these optional properties and there do not appear to be any GIC instances that define these. To support GICs that require runtime power management and hence, define the clock and/or power-domain properties, a platform driver for GICs using power management will be added. However, this presents a problem because by adding a platform driver in addition to the current GIC driver, we will have two places where we can match the GIC compatibility string to initialise the GIC and these are: 1. By the IRQCHIP_DECLARE macro for early initialisation of GICs. 2. By the platform driver's device-tree match table. To prevent a GIC which requires power management from being initialised early (by matching the compatibility string specified by IRQCHIP_DECLARE), during early inialisation, if we detect the GIC has either the 'clocks' or 'power-domains' property present bail out of the early initialisation and allow the platform driver to initialise the device. Signed-off-by: Jon Hunter --- drivers/irqchip/irq-gic.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 30666f349649..a10274926690 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -1205,6 +1205,15 @@ gic_of_init(struct device_node *node, struct device_node *parent) if (WARN_ON(!node)) return -ENODEV; + /* + * If the GIC device has either a 'clocks' node or a 'power-domains' + * node populated, then bail out now because this driver is currently + * unable to support devices which require power management. + */ + if (of_property_read_bool(node, "clocks") || + of_property_read_bool(node, "power-domains")) + return 0; + dist_base = of_iomap(node, 0); if (WARN(!dist_base, "unable to map gic dist registers\n")) return -ENOMEM;