From patchwork Wed May 4 16:25:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 9016581 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id ED07F9F30C for ; Wed, 4 May 2016 16:29:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1FB612026D for ; Wed, 4 May 2016 16:29:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8B20F203C0 for ; Wed, 4 May 2016 16:29:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754412AbcEDQ0r (ORCPT ); Wed, 4 May 2016 12:26:47 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:4770 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754364AbcEDQ0p (ORCPT ); Wed, 4 May 2016 12:26:45 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Wed, 04 May 2016 09:26:12 -0700 Received: from HQMAIL103.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 04 May 2016 09:26:06 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 04 May 2016 09:26:06 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Wed, 4 May 2016 16:26:44 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Wed, 4 May 2016 16:26:43 +0000 Received: from jonathanh-lm.nvidia.com (Not Verified[10.21.132.133]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Wed, 04 May 2016 09:26:43 -0700 From: Jon Hunter To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Stephen Warren , Thierry Reding CC: Kevin Hilman , Geert Uytterhoeven , Grygorii Strashko , Lars-Peter Clausen , Linus Walleij , , , , , Jon Hunter Subject: [PATCH V3 14/17] irqchip/gic: Add helper function for configuring a GIC via device-tree Date: Wed, 4 May 2016 17:25:27 +0100 Message-ID: <1462379130-11742-15-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1462379130-11742-1-git-send-email-jonathanh@nvidia.com> References: <1462379130-11742-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Move the code that configures a GIC via device-tree into it's own function. This will allow us to re-use this function when adding a platform driver to support GICs that require power-management. Signed-off-by: Jon Hunter --- drivers/irqchip/irq-gic.c | 37 +++++++++++++++++++++++++------------ 1 file changed, 25 insertions(+), 12 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index a10274926690..2fc5018d6eb9 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -1194,6 +1194,28 @@ static bool gic_check_eoimode(struct device_node *node, void __iomem **base) return true; } +static int gic_of_setup(struct device_node *node, void __iomem **dist_base, + void __iomem **cpu_base, u32 *percpu_offset) +{ + if (!node || !dist_base || !cpu_base || !percpu_offset) + return -EINVAL; + + *dist_base = of_iomap(node, 0); + if (WARN(!*dist_base, "unable to map gic dist registers\n")) + return -ENOMEM; + + *cpu_base = of_iomap(node, 1); + if (WARN(!*cpu_base, "unable to map gic cpu registers\n")) { + iounmap(*dist_base); + return -ENOMEM; + } + + if (of_property_read_u32(node, "cpu-offset", percpu_offset)) + *percpu_offset = 0; + + return 0; +} + int __init gic_of_init(struct device_node *node, struct device_node *parent) { @@ -1214,15 +1236,9 @@ gic_of_init(struct device_node *node, struct device_node *parent) of_property_read_bool(node, "power-domains")) return 0; - dist_base = of_iomap(node, 0); - if (WARN(!dist_base, "unable to map gic dist registers\n")) - return -ENOMEM; - - cpu_base = of_iomap(node, 1); - if (WARN(!cpu_base, "unable to map gic cpu registers\n")) { - iounmap(dist_base); - return -ENOMEM; - } + ret = gic_of_setup(node, &dist_base, &cpu_base, &percpu_offset); + if (ret) + return ret; /* * Disable split EOI/Deactivate if either HYP is not available @@ -1231,9 +1247,6 @@ gic_of_init(struct device_node *node, struct device_node *parent) if (gic_cnt == 0 && !gic_check_eoimode(node, &cpu_base)) static_key_slow_dec(&supports_deactivate); - if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) - percpu_offset = 0; - ret = __gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, &node->fwnode); if (ret) {