From patchwork Wed May 4 16:25:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 9016561 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 153D3BF29F for ; Wed, 4 May 2016 16:28:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 18845202E9 for ; Wed, 4 May 2016 16:28:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 856F12026D for ; Wed, 4 May 2016 16:28:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754463AbcEDQ0v (ORCPT ); Wed, 4 May 2016 12:26:51 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:4793 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754445AbcEDQ0t (ORCPT ); Wed, 4 May 2016 12:26:49 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Wed, 04 May 2016 09:26:17 -0700 Received: from HQMAIL103.nvidia.com ([172.20.187.11]) by hqnvupgp07.nvidia.com (PGP Universal service); Wed, 04 May 2016 09:25:42 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Wed, 04 May 2016 09:25:42 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Wed, 4 May 2016 16:26:48 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Wed, 4 May 2016 16:26:47 +0000 Received: from jonathanh-lm.nvidia.com (Not Verified[10.21.132.133]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Wed, 04 May 2016 09:26:47 -0700 From: Jon Hunter To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Stephen Warren , Thierry Reding CC: Kevin Hilman , Geert Uytterhoeven , Grygorii Strashko , Lars-Peter Clausen , Linus Walleij , , , , , Jon Hunter Subject: [PATCH V3 15/17] irqchip/gic: Split GIC init in preparation for platform driver Date: Wed, 4 May 2016 17:25:28 +0100 Message-ID: <1462379130-11742-16-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1462379130-11742-1-git-send-email-jonathanh@nvidia.com> References: <1462379130-11742-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP To re-use the code that initialises the GIC (found in __gic_init_bases()), from within a platform driver, it is necessary to move the code from the __init section so that it is always present and not removed. Unfortunately, it is not possible to simply drop the __init from the function declaration for __gic_init_bases() because it contains calls to set_smp_cross_call() and set_handle_irq() which are both located in the __init section. Fortunately, these calls are only required for the root controller and because the initial platform driver will only support non-root controllers that can be initialised later in the boot process, we can move these calls to another function. Move the bulk of the code from __gic_init_bases() to a new function called gic_init_bases() which is not located in the __init section and can be used by the platform driver. Update __gic_init_bases() to call gic_init_bases() and if necessary, set_smp_cross_call() and set_handle_irq(). To allow the platform driver to dynamically allocate the GIC chip data structure, rather than passing an index to reference the GIC to gic_init_bases() pass a pointer to the chip data instead. This means that the name must be passed to gic_init_bases() as well, because the name will not be passed upon an index for a platform device. Signed-off-by: Jon Hunter --- drivers/irqchip/irq-gic.c | 71 +++++++++++++++++++++++++++++++---------------- 1 file changed, 47 insertions(+), 24 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 2fc5018d6eb9..15e8a12813cc 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -1002,32 +1002,29 @@ static const struct irq_domain_ops gic_irq_domain_ops = { .unmap = gic_irq_domain_unmap, }; -static int __init __gic_init_bases(unsigned int gic_nr, int irq_start, - void __iomem *dist_base, void __iomem *cpu_base, - u32 percpu_offset, struct fwnode_handle *handle) +static int gic_init_bases(struct gic_chip_data *gic, int irq_start, + void __iomem *dist_base, void __iomem *cpu_base, + u32 percpu_offset, struct fwnode_handle *handle, + const char *name) { irq_hw_number_t hwirq_base; - struct gic_chip_data *gic; - int gic_irqs, irq_base, i, ret; - - BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); + int gic_irqs, irq_base, ret; - gic = &gic_data[gic_nr]; + if (WARN_ON(!gic || gic->domain)) + return -EINVAL; /* Initialize irq_chip */ gic->chip = gic_chip; + gic->chip.name = name; - if (static_key_true(&supports_deactivate) && gic_nr == 0) { + if (static_key_true(&supports_deactivate) && gic == &gic_data[0]) { gic->chip.irq_mask = gic_eoimode1_mask_irq; gic->chip.irq_eoi = gic_eoimode1_eoi_irq; gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity; - gic->chip.name = kasprintf(GFP_KERNEL, "GICv2"); - } else { - gic->chip.name = kasprintf(GFP_KERNEL, "GIC-%d", gic_nr); } #ifdef CONFIG_SMP - if (gic_nr == 0) + if (gic == &gic_data[0]) gic->chip.irq_set_affinity = gic_set_affinity; #endif @@ -1081,7 +1078,7 @@ static int __init __gic_init_bases(unsigned int gic_nr, int irq_start, * For primary GICs, skip over SGIs. * For secondary GICs, skip over PPIs, too. */ - if (gic_nr == 0 && (irq_start & 31) > 0) { + if (gic == &gic_data[0] && (irq_start & 31) > 0) { hwirq_base = 16; if (irq_start != -1) irq_start = (irq_start & ~31) + 16; @@ -1108,6 +1105,42 @@ static int __init __gic_init_bases(unsigned int gic_nr, int irq_start, goto error; } + return 0; + +error: + if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && percpu_offset) { + free_percpu(gic->dist_base.percpu_base); + free_percpu(gic->cpu_base.percpu_base); + } + + return ret; +} + +static int __init __gic_init_bases(unsigned int gic_nr, int irq_start, + void __iomem *dist_base, void __iomem *cpu_base, + u32 percpu_offset, struct fwnode_handle *handle) +{ + struct gic_chip_data *gic; + char *name; + int i, ret; + + if (WARN_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR)) + return -EINVAL; + + gic = &gic_data[gic_nr]; + + if (static_key_true(&supports_deactivate) && gic_nr == 0) + name = kasprintf(GFP_KERNEL, "GICv2"); + else + name = kasprintf(GFP_KERNEL, "GIC-%d", gic_nr); + + ret = gic_init_bases(gic, irq_start, dist_base, cpu_base, percpu_offset, + handle, name); + if (ret) { + kfree(name); + return ret; + } + if (gic_nr == 0) { /* * Initialize the CPU interface map to all CPUs. @@ -1130,16 +1163,6 @@ static int __init __gic_init_bases(unsigned int gic_nr, int irq_start, gic_pm_init(gic); return 0; - -error: - if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && percpu_offset) { - free_percpu(gic->dist_base.percpu_base); - free_percpu(gic->cpu_base.percpu_base); - } - - kfree(gic->chip.name); - - return ret; } void __init gic_init(unsigned int gic_nr, int irq_start,