From patchwork Mon May 9 21:49:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Gerlach X-Patchwork-Id: 9050181 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id F1157BF29F for ; Mon, 9 May 2016 21:50:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 10FA92012D for ; Mon, 9 May 2016 21:50:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 12004200F3 for ; Mon, 9 May 2016 21:50:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753115AbcEIVuI (ORCPT ); Mon, 9 May 2016 17:50:08 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:50816 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752739AbcEIVuH (ORCPT ); Mon, 9 May 2016 17:50:07 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id u49LnhX7020755; Mon, 9 May 2016 16:49:43 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id u49LnhHr020092; Mon, 9 May 2016 16:49:43 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.224.2; Mon, 9 May 2016 16:49:43 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u49LngNB027959; Mon, 9 May 2016 16:49:43 -0500 Received: from localhost (uda0274052.am.dhcp.ti.com [128.247.83.19]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id u49Lng305068; Mon, 9 May 2016 16:49:42 -0500 (CDT) From: Dave Gerlach To: , CC: Tony Lindgren , Dave Gerlach Subject: [PATCH 1/6] Documentation: sram: ti: Add TI SRAM bindings Date: Mon, 9 May 2016 16:49:21 -0500 Message-ID: <1462830566-28708-2-git-send-email-d-gerlach@ti.com> X-Mailer: git-send-email 2.7.3 In-Reply-To: <1462830566-28708-1-git-send-email-d-gerlach@ti.com> References: <1462830566-28708-1-git-send-email-d-gerlach@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add binding document for TI use of mmio-sram driver for purposes like mapping the region as executable or reserving space needed by secure silicon. Signed-off-by: Dave Gerlach --- Documentation/devicetree/bindings/sram/ti-sram.txt | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/sram/ti-sram.txt diff --git a/Documentation/devicetree/bindings/sram/ti-sram.txt b/Documentation/devicetree/bindings/sram/ti-sram.txt new file mode 100644 index 000000000000..68c4b733c78c --- /dev/null +++ b/Documentation/devicetree/bindings/sram/ti-sram.txt @@ -0,0 +1,47 @@ +TI SRAM Node: +------------- + +Many TI SoC's rely on SRAM for running low-level PM code as part of the +suspend or cpuidle path. Because of this, regions in sram must be mapped +as "memory-exec" or "memory-exec-nocache" in order for the region to be +executable. + +Optional sub-node +----------------- +Some TI SoCs have secure variants that require a certain portion of +the SRAM to be reserved for use by secure software. This can be +marked in the parent SRAM node with a subnode as described in +Documentation/devicetree/bindings/sram/sram.txt. This node can be +added in two ways: + +- From board dts files for secure platforms to avoid adding it + for all SoC variants with a fixed size defined. +- As a dummy node in the .dtsi sram node with any size that will be + modified by a bootloader to the correct size needed. + +Sub-node properties: +- compatible : should be "ti,secure-sram" + +The rest of the properties should follow the generic mmio-sram discription +found in Documentation/devicetree/bindings/sram/sram.txt + +Example: + /* In parent SoC .dtsi */ + ocmcram: ocmcram@40200000 { + compatible = "mmio-sram"; + reg = <0x40200000 0x10000>; /* 64k */ + memory-exec-nocache; + ranges = <0x0 0x40200000 0x10000>; + + #address-cells = <1>; + #size-cells = <1>; + + }; + + /* In board .dts where secure silicon is present */ + &ocmcram { + sram-hs@0 { + compatible = "ti,secure-ram"; + reg = <0x0 0xC000>; + }; + };