From patchwork Tue May 10 19:49:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Gerlach X-Patchwork-Id: 9061461 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8780BBF29F for ; Tue, 10 May 2016 19:50:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 907DE20173 for ; Tue, 10 May 2016 19:50:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 974FD20165 for ; Tue, 10 May 2016 19:50:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752767AbcEJTuX (ORCPT ); Tue, 10 May 2016 15:50:23 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:46632 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752268AbcEJTuU (ORCPT ); Tue, 10 May 2016 15:50:20 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id u4AJnnn3029924; Tue, 10 May 2016 14:49:49 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u4AJnna1013917; Tue, 10 May 2016 14:49:49 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.224.2; Tue, 10 May 2016 14:49:49 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id u4AJnnBu014348; Tue, 10 May 2016 14:49:49 -0500 Received: from localhost (uda0274052.am.dhcp.ti.com [128.247.83.19]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id u4AJnn317539; Tue, 10 May 2016 14:49:49 -0500 (CDT) From: Dave Gerlach To: , , CC: Andreas Dannenberg , Suman Anna , Rob Herring , Mark Rutland , Tony Lindgren , Dave Gerlach Subject: [PATCH 2/2] ARM: dts: dra7: Add ti, secure-ram node to ocmcram1 node Date: Tue, 10 May 2016 14:49:42 -0500 Message-ID: <1462909782-14639-3-git-send-email-d-gerlach@ti.com> X-Mailer: git-send-email 2.7.3 In-Reply-To: <1462909782-14639-1-git-send-email-d-gerlach@ti.com> References: <1462909782-14639-1-git-send-email-d-gerlach@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Secure variants of DRA7xx and AM57xx SoCs may need to reserve a region of the SRAM for use by secure software. To account for this, add a child node to the ocmcram1 node that will act as a placeholder at the start of the SRAM for the reserved region of memory that may be required by secure services. The node is added with size 0 so that by default parts will have the full space available but the bootloader or board dts file is able to resize the node as needed depending on how much reserved space is needed, if any, so end users of the ocmcram1 region on HS parts must be aware that a smaller amount of SRAM than expected may be available. Signed-off-by: Dave Gerlach Reviewed-by: Andreas Dannenberg --- arch/arm/boot/dts/dra7.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index fd6f74856bd3..f46a265ce315 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -292,6 +292,21 @@ ranges = <0x0 0x40300000 0x80000>; #address-cells = <1>; #size-cells = <1>; + /* + * This is a placeholder for an optional reserved + * region for use by secure software. The size + * of this region is not known until runtime so it + * is set as zero to either be updated to reserve + * space or left unchanged to leave all SRAM for use. + * On HS parts that that require the reserved region + * either the bootloader can update the size to + * the required amount or the node can be overridden + * from the board dts file for the secure platform. + */ + sram-hs@0 { + compatible = "ti,secure-ram"; + reg = <0x0 0x0>; + }; }; /*