From patchwork Tue Nov 8 13:10:56 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ivan Khoronzhuk X-Patchwork-Id: 9417331 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D6F026022E for ; Tue, 8 Nov 2016 13:11:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C90BE28713 for ; Tue, 8 Nov 2016 13:11:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BDFC428F7D; Tue, 8 Nov 2016 13:11:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.3 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4296028713 for ; Tue, 8 Nov 2016 13:11:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753339AbcKHNLE (ORCPT ); Tue, 8 Nov 2016 08:11:04 -0500 Received: from mail-lf0-f46.google.com ([209.85.215.46]:35918 "EHLO mail-lf0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753336AbcKHNLC (ORCPT ); Tue, 8 Nov 2016 08:11:02 -0500 Received: by mail-lf0-f46.google.com with SMTP id t196so139257127lff.3 for ; Tue, 08 Nov 2016 05:11:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=CqytF9ZX34KdJgP71RcksPogrcqSApy9YARw3O1lhc8=; b=FRBoQZMrz/lR3nJJeiP3hPnRXnlf2PqPPubATWCqravJOdENcmj/BaCn1pYmGuRDjS frLTbGAy147+d3MQR+f/p/7CXHbUQLjNpcjMaF6d5X2w8BXStSb3XOioRh8k5u8OZrNA G6ueDTqUYP6jNg+pU/ufBlvnda5BDv+mFjg/g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=CqytF9ZX34KdJgP71RcksPogrcqSApy9YARw3O1lhc8=; b=jVeD9ed00lqp/nY1hnhwpSSmDXPYhdFppDPdNG/xPkIsgI0U5jHFGP6iy/aZncN1Ij vNuln+SGOsAplCTyWn0reEUeHWjenTBQtSxPH+ZCwduG0kauWY02t8mKPpFTd0R7C8fr lDiZjyVe6e8MLX4QUT9Htzs3NbTYqzsiO7uixmmMjOHqqXFk2IrjjaI1sutDDBOD3BQ4 Hbj1/6D5aHyTNk3tcKdiYvNH1m6pkJ3LlkeKpIwp4q8us9wFxRxbiDaj9PQM9rm2xX4M rroDkmZa4JlwMvN8zuOuSUG0Xepx1RqoKIjvIJVvchGjM1zGBL6ddH5VEop2/qiOjawL wdYw== X-Gm-Message-State: ABUngvee+T5xEU+n6NXyiNO29JOzutLZuL+0S0cuBhdhe2VCAijzltTZfPV0dYCVkFXN6Ntl X-Received: by 10.25.212.77 with SMTP id l74mr5498369lfg.103.1478610660668; Tue, 08 Nov 2016 05:11:00 -0800 (PST) Received: from localhost.localdomain (167-203-94-178.pool.ukrtel.net. [178.94.203.167]) by smtp.gmail.com with ESMTPSA id g38sm4664445lfi.40.2016.11.08.05.10.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 08 Nov 2016 05:11:00 -0800 (PST) From: Ivan Khoronzhuk To: mugunthanvnm@ti.com, grygorii.strashko@ti.com, netdev@vger.kernel.org Cc: linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org, Ivan Khoronzhuk Subject: [PATCH] net: ethernet: ti: davinci_cpdma: fix fixed prio cpdma ctlr configuration Date: Tue, 8 Nov 2016 15:10:56 +0200 Message-Id: <1478610656-24634-1-git-send-email-ivan.khoronzhuk@linaro.org> X-Mailer: git-send-email 1.9.1 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The dma ctlr is reseted to 0 while cpdma start, thus cpdma ctlr cannot be configured after cpdma is stopped. So, restore content of cpdma ctlr while off/on procedure. Based on net-next/master Signed-off-by: Ivan Khoronzhuk --- drivers/net/ethernet/ti/cpsw.c | 6 +- drivers/net/ethernet/ti/davinci_cpdma.c | 103 +++++++++++++++++--------------- drivers/net/ethernet/ti/davinci_cpdma.h | 2 + 3 files changed, 58 insertions(+), 53 deletions(-) diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index b1ddf89..4d04b8e 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -1376,10 +1376,6 @@ static int cpsw_ndo_open(struct net_device *ndev) ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0); if (!cpsw_common_res_usage_state(cpsw)) { - /* setup tx dma to fixed prio and zero offset */ - cpdma_control_set(cpsw->dma, CPDMA_TX_PRIO_FIXED, 1); - cpdma_control_set(cpsw->dma, CPDMA_RX_BUFFER_OFFSET, 0); - /* disable priority elevation */ __raw_writel(0, &cpsw->regs->ptype); @@ -2710,6 +2706,8 @@ static int cpsw_probe(struct platform_device *pdev) dma_params.desc_align = 16; dma_params.has_ext_regs = true; dma_params.desc_hw_addr = dma_params.desc_mem_phys; + dma_params.rxbuf_offset = 0; + dma_params.fixed_prio = 1; cpsw->dma = cpdma_ctlr_create(&dma_params); if (!cpsw->dma) { diff --git a/drivers/net/ethernet/ti/davinci_cpdma.c b/drivers/net/ethernet/ti/davinci_cpdma.c index c3f35f1..05afc05 100644 --- a/drivers/net/ethernet/ti/davinci_cpdma.c +++ b/drivers/net/ethernet/ti/davinci_cpdma.c @@ -124,6 +124,29 @@ struct cpdma_chan { int int_set, int_clear, td; }; +struct cpdma_control_info { + u32 reg; + u32 shift, mask; + int access; +#define ACCESS_RO BIT(0) +#define ACCESS_WO BIT(1) +#define ACCESS_RW (ACCESS_RO | ACCESS_WO) +}; + +static struct cpdma_control_info controls[] = { + [CPDMA_CMD_IDLE] = {CPDMA_DMACONTROL, 3, 1, ACCESS_WO}, + [CPDMA_COPY_ERROR_FRAMES] = {CPDMA_DMACONTROL, 4, 1, ACCESS_RW}, + [CPDMA_RX_OFF_LEN_UPDATE] = {CPDMA_DMACONTROL, 2, 1, ACCESS_RW}, + [CPDMA_RX_OWNERSHIP_FLIP] = {CPDMA_DMACONTROL, 1, 1, ACCESS_RW}, + [CPDMA_TX_PRIO_FIXED] = {CPDMA_DMACONTROL, 0, 1, ACCESS_RW}, + [CPDMA_STAT_IDLE] = {CPDMA_DMASTATUS, 31, 1, ACCESS_RO}, + [CPDMA_STAT_TX_ERR_CODE] = {CPDMA_DMASTATUS, 20, 0xf, ACCESS_RW}, + [CPDMA_STAT_TX_ERR_CHAN] = {CPDMA_DMASTATUS, 16, 0x7, ACCESS_RW}, + [CPDMA_STAT_RX_ERR_CODE] = {CPDMA_DMASTATUS, 12, 0xf, ACCESS_RW}, + [CPDMA_STAT_RX_ERR_CHAN] = {CPDMA_DMASTATUS, 8, 0x7, ACCESS_RW}, + [CPDMA_RX_BUFFER_OFFSET] = {CPDMA_RXBUFFOFS, 0, 0xffff, ACCESS_RW}, +}; + #define tx_chan_num(chan) (chan) #define rx_chan_num(chan) ((chan) + CPDMA_MAX_CHANNELS) #define is_rx_chan(chan) ((chan)->chan_num >= CPDMA_MAX_CHANNELS) @@ -253,6 +276,31 @@ static void cpdma_desc_free(struct cpdma_desc_pool *pool, gen_pool_free(pool->gen_pool, (unsigned long)desc, pool->desc_size); } +static int _cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value) +{ + struct cpdma_control_info *info = &controls[control]; + u32 val; + + if (!ctlr->params.has_ext_regs) + return -ENOTSUPP; + + if (ctlr->state != CPDMA_STATE_ACTIVE) + return -EINVAL; + + if (control < 0 || control >= ARRAY_SIZE(controls)) + return -ENOENT; + + if ((info->access & ACCESS_WO) != ACCESS_WO) + return -EPERM; + + val = dma_reg_read(ctlr, info->reg); + val &= ~(info->mask << info->shift); + val |= (value & info->mask) << info->shift; + dma_reg_write(ctlr, info->reg, val); + + return 0; +} + struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params) { struct cpdma_ctlr *ctlr; @@ -324,6 +372,11 @@ int cpdma_ctlr_start(struct cpdma_ctlr *ctlr) if (ctlr->channels[i]) cpdma_chan_start(ctlr->channels[i]); } + + _cpdma_control_set(ctlr, CPDMA_TX_PRIO_FIXED, ctlr->params.fixed_prio); + _cpdma_control_set(ctlr, CPDMA_RX_BUFFER_OFFSET, + ctlr->params.rxbuf_offset); + spin_unlock_irqrestore(&ctlr->lock, flags); return 0; } @@ -874,29 +927,6 @@ int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable) return 0; } -struct cpdma_control_info { - u32 reg; - u32 shift, mask; - int access; -#define ACCESS_RO BIT(0) -#define ACCESS_WO BIT(1) -#define ACCESS_RW (ACCESS_RO | ACCESS_WO) -}; - -static struct cpdma_control_info controls[] = { - [CPDMA_CMD_IDLE] = {CPDMA_DMACONTROL, 3, 1, ACCESS_WO}, - [CPDMA_COPY_ERROR_FRAMES] = {CPDMA_DMACONTROL, 4, 1, ACCESS_RW}, - [CPDMA_RX_OFF_LEN_UPDATE] = {CPDMA_DMACONTROL, 2, 1, ACCESS_RW}, - [CPDMA_RX_OWNERSHIP_FLIP] = {CPDMA_DMACONTROL, 1, 1, ACCESS_RW}, - [CPDMA_TX_PRIO_FIXED] = {CPDMA_DMACONTROL, 0, 1, ACCESS_RW}, - [CPDMA_STAT_IDLE] = {CPDMA_DMASTATUS, 31, 1, ACCESS_RO}, - [CPDMA_STAT_TX_ERR_CODE] = {CPDMA_DMASTATUS, 20, 0xf, ACCESS_RW}, - [CPDMA_STAT_TX_ERR_CHAN] = {CPDMA_DMASTATUS, 16, 0x7, ACCESS_RW}, - [CPDMA_STAT_RX_ERR_CODE] = {CPDMA_DMASTATUS, 12, 0xf, ACCESS_RW}, - [CPDMA_STAT_RX_ERR_CHAN] = {CPDMA_DMASTATUS, 8, 0x7, ACCESS_RW}, - [CPDMA_RX_BUFFER_OFFSET] = {CPDMA_RXBUFFOFS, 0, 0xffff, ACCESS_RW}, -}; - int cpdma_control_get(struct cpdma_ctlr *ctlr, int control) { unsigned long flags; @@ -931,35 +961,10 @@ int cpdma_control_get(struct cpdma_ctlr *ctlr, int control) int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value) { unsigned long flags; - struct cpdma_control_info *info = &controls[control]; int ret; - u32 val; spin_lock_irqsave(&ctlr->lock, flags); - - ret = -ENOTSUPP; - if (!ctlr->params.has_ext_regs) - goto unlock_ret; - - ret = -EINVAL; - if (ctlr->state != CPDMA_STATE_ACTIVE) - goto unlock_ret; - - ret = -ENOENT; - if (control < 0 || control >= ARRAY_SIZE(controls)) - goto unlock_ret; - - ret = -EPERM; - if ((info->access & ACCESS_WO) != ACCESS_WO) - goto unlock_ret; - - val = dma_reg_read(ctlr, info->reg); - val &= ~(info->mask << info->shift); - val |= (value & info->mask) << info->shift; - dma_reg_write(ctlr, info->reg, val); - ret = 0; - -unlock_ret: + ret = _cpdma_control_set(ctlr, control, value); spin_unlock_irqrestore(&ctlr->lock, flags); return ret; } diff --git a/drivers/net/ethernet/ti/davinci_cpdma.h b/drivers/net/ethernet/ti/davinci_cpdma.h index a07b22b..e66420f 100644 --- a/drivers/net/ethernet/ti/davinci_cpdma.h +++ b/drivers/net/ethernet/ti/davinci_cpdma.h @@ -31,6 +31,8 @@ struct cpdma_params { void __iomem *rxthresh, *rxfree; int num_chan; bool has_soft_reset; + bool fixed_prio; + int rxbuf_offset; int min_packet_size; u32 desc_mem_phys; u32 desc_hw_addr;