From patchwork Mon Mar 13 16:43:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 9621551 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 10A0660522 for ; Mon, 13 Mar 2017 16:50:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 01A59284CF for ; Mon, 13 Mar 2017 16:50:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EA59D284F1; Mon, 13 Mar 2017 16:50:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8D499284D1 for ; Mon, 13 Mar 2017 16:50:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754213AbdCMQqq (ORCPT ); Mon, 13 Mar 2017 12:46:46 -0400 Received: from mail-wr0-f169.google.com ([209.85.128.169]:33370 "EHLO mail-wr0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754245AbdCMQoP (ORCPT ); Mon, 13 Mar 2017 12:44:15 -0400 Received: by mail-wr0-f169.google.com with SMTP id u48so107670274wrc.0 for ; Mon, 13 Mar 2017 09:43:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Cmqg0SiHNyGVSd4tLDqHZCxDO4ZbHcrJbpQdgSpzmSw=; b=bfXQVn3K2YqfwCVki69XwbqEcfPfXRqnf76OlZaueA9SmQvH4buDyyxjlZUkY84SVa 9tFQWfD3k8TrByp5DnHBulEW/MaK504iyVxN/Jpf39v97c7I5uTa7kidwWLM+v8alqQX gRBYqZ2bgaNxRrKcuSHugwpGFI8KPEpYsPKn4NMAJP6tQ5rR88M/LZ29O2I+FYoI/SiG +9RjSeiqcD1UcQzdqFrcrWxONA5iJEb1LRcGHOHGqN+VEK5VmkIJbBLHbiJTFfa7nviT 4RYZ0Vd4Ldp6IZ2oB7kGskFS3rOtvAs2jvojE5Uy8D+AocP5sMRlijvXr/0uOC/bBe1e dwmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Cmqg0SiHNyGVSd4tLDqHZCxDO4ZbHcrJbpQdgSpzmSw=; b=N2F2gXbQCc1nZeg6THyf+ia2DNfkhsAPyqpGCJMpi9K6vFA7NDH4wjThGzaWbKeR9E qf2+i9mILg1EHjCJiN4CdK0e6RsUi/Ire7YCCZbLwDLHSP7VLMo6bKcJnobBqIoQ0r1G vFkUUV3nmttjMCu9F9gVTbVNp7zyRQuMaxe1YiPPkQ/YhA1xoVROvE9wab4ap3V5TvKh CkbKdCE3ex43Pth7Uq0amL+8oJZnI+bVBCrCxTrvcV9EA8lrA4PCcrTq+ZmsIOUygdpu 39p0D4I4ZxHNmvnOn67n4czrihZNZxsCxyxXufG/aRTkoWfb/zrx1za1sGY+9lMfKK4r 7brg== X-Gm-Message-State: AMke39lkhj93cIdigRBJMbUVIdBt6hgoKtHas18Olj+X1lKfvO4g3JkcB3pICPI2dC2/NJyS X-Received: by 10.223.168.80 with SMTP id l74mr29413504wrc.184.1489423411630; Mon, 13 Mar 2017 09:43:31 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.gmail.com with ESMTPSA id g45sm25594602wrd.11.2017.03.13.09.43.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 13 Mar 2017 09:43:31 -0700 (PDT) From: Bartosz Golaszewski To: Rob Herring , Mark Rutland , Neil Armstrong , Michael Turquette , Kevin Hilman , Patrick Titiano , Tony Lindgren , Paul Walmsley Cc: linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-omap@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH 1/4] ARM: OMAP2+: dm81xx: Add clkdm and hwmod for SATA Date: Mon, 13 Mar 2017 17:43:16 +0100 Message-Id: <1489423399-3824-2-git-send-email-bgolaszewski@baylibre.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1489423399-3824-1-git-send-email-bgolaszewski@baylibre.com> References: <1489423399-3824-1-git-send-email-bgolaszewski@baylibre.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Kevin Hilman Add the SATA clockdomain (part of CM_DEFAULT) and a hwmod for the SATA block on dm81xx. Tested on DM8168 EVM. Signed-off-by: Kevin Hilman Signed-off-by: Bartosz Golaszewski --- arch/arm/mach-omap2/clockdomains81xx_data.c | 10 +++++++++ arch/arm/mach-omap2/cm81xx.h | 2 ++ arch/arm/mach-omap2/omap_hwmod_81xx_data.c | 34 +++++++++++++++++++++++++++++ 3 files changed, 46 insertions(+) diff --git a/arch/arm/mach-omap2/clockdomains81xx_data.c b/arch/arm/mach-omap2/clockdomains81xx_data.c index 3b5fb05..65fbd13 100644 --- a/arch/arm/mach-omap2/clockdomains81xx_data.c +++ b/arch/arm/mach-omap2/clockdomains81xx_data.c @@ -91,6 +91,14 @@ static struct clockdomain default_l3_slow_81xx_clkdm = { .flags = CLKDM_CAN_SWSUP, }; +static struct clockdomain default_sata_81xx_clkdm = { + .name = "default_clkdm", + .pwrdm = { .name = "default_pwrdm" }, + .cm_inst = TI81XX_CM_DEFAULT_MOD, + .clkdm_offs = TI816X_CM_DEFAULT_SATA_CLKDM, + .flags = CLKDM_CAN_SWSUP, +}; + /* 816x only */ static struct clockdomain alwon_mpu_816x_clkdm = { @@ -173,6 +181,7 @@ static struct clockdomain *clockdomains_ti814x[] __initdata = { &mmu_81xx_clkdm, &mmu_cfg_81xx_clkdm, &default_l3_slow_81xx_clkdm, + &default_sata_81xx_clkdm, NULL, }; @@ -200,6 +209,7 @@ static struct clockdomain *clockdomains_ti816x[] __initdata = { &default_ducati_816x_clkdm, &default_pci_816x_clkdm, &default_l3_slow_81xx_clkdm, + &default_sata_81xx_clkdm, NULL, }; diff --git a/arch/arm/mach-omap2/cm81xx.h b/arch/arm/mach-omap2/cm81xx.h index 3a0ccf0..44ca275 100644 --- a/arch/arm/mach-omap2/cm81xx.h +++ b/arch/arm/mach-omap2/cm81xx.h @@ -35,6 +35,7 @@ #define TI81XX_CM_MMU_CLKDM 0x000C #define TI81XX_CM_MMUCFG_CLKDM 0x0010 #define TI81XX_CM_ALWON_MPU_CLKDM 0x001C +#define TI81XX_CM_ALWON_SYSCLK5_CLKDM 0x0024 #define TI81XX_CM_ALWON_L3_FAST_CLKDM 0x0030 /* ACTIVE */ @@ -57,5 +58,6 @@ #define TI816X_CM_DEFAULT_PCI_CLKDM 0x0010 #define TI816X_CM_DEFAULT_L3_SLOW_CLKDM 0x0014 #define TI816X_CM_DEFAULT_DUCATI_CLKDM 0x0018 +#define TI816X_CM_DEFAULT_SATA_CLKDM 0x0060 #endif diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c index b82b77c..310afe4 100644 --- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c @@ -106,6 +106,7 @@ */ #define DM81XX_CM_DEFAULT_OFFSET 0x500 #define DM81XX_CM_DEFAULT_USB_CLKCTRL (0x558 - DM81XX_CM_DEFAULT_OFFSET) +#define DM81XX_CM_DEFAULT_SATA_CLKCTRL (0x560 - DM81XX_CM_DEFAULT_OFFSET) /* L3 Interconnect entries clocked at 125, 250 and 500MHz */ static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = { @@ -973,6 +974,38 @@ static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = { .user = OCP_USER_MPU, }; +static struct omap_hwmod_class_sysconfig dm81xx_sata_sysc = { + .sysc_offs = 0x1100, + .sysc_flags = SYSC_HAS_SIDLEMODE, + .idlemodes = SIDLE_FORCE, + .sysc_fields = &omap_hwmod_sysc_type3, +}; + +static struct omap_hwmod_class dm81xx_sata_hwmod_class = { + .name = "sata", + .sysc = &dm81xx_sata_sysc, +}; + +static struct omap_hwmod dm81xx_sata_hwmod = { + .name = "sata", + .clkdm_name = "default_sata_clkdm", + .flags = HWMOD_NO_IDLEST, + .prcm = { + .omap4 = { + .clkctrl_offs = DM81XX_CM_DEFAULT_SATA_CLKCTRL, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .class = &dm81xx_sata_hwmod_class, +}; + +static struct omap_hwmod_ocp_if dm81xx_l4_hs__sata = { + .master = &dm81xx_l4_hs_hwmod, + .slave = &dm81xx_sata_hwmod, + .clk = "sysclk5_ck", + .user = OCP_USER_MPU, +}; + static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = { .rev_offs = 0x0, .sysc_offs = 0x110, @@ -1474,6 +1507,7 @@ static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = { &dm81xx_l4_hs__emac0, &dm81xx_emac0__mdio, &dm816x_l4_hs__emac1, + &dm81xx_l4_hs__sata, &dm81xx_alwon_l3_fast__tpcc, &dm81xx_alwon_l3_fast__tptc0, &dm81xx_alwon_l3_fast__tptc1,