From patchwork Wed Sep 27 12:25:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "J, KEERTHY" X-Patchwork-Id: 9973939 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 40B7A6037F for ; Wed, 27 Sep 2017 12:26:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3863F28FD9 for ; Wed, 27 Sep 2017 12:26:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2D452290FA; Wed, 27 Sep 2017 12:26:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9162228FD9 for ; Wed, 27 Sep 2017 12:26:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752815AbdI0M0C (ORCPT ); Wed, 27 Sep 2017 08:26:02 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:44638 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751671AbdI0MZ7 (ORCPT ); Wed, 27 Sep 2017 08:25:59 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8RCPuBN005333; Wed, 27 Sep 2017 07:25:56 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1506515156; bh=kFHP9GJWzos521uLonFlbX5csDJ/K5wIZ+C5s3hKZaU=; h=From:To:CC:Subject:Date; b=SHSCaVLuGensJIAB1BiLnDmVp7JSUnJtnhyHu0MiBvEWMiqotFWs6GDIoiOe/SOyT FfENXC096xkBEXC7KN1at3/ZGZ4PHw9uVlvdb2NOnyZY5qJPJUowNRx21/I4JM7uE8 1tEpvYEnoMWcPjH8ABLBx+G7iCf4bmsGqFVwrfWs= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8RCPu9C012999; Wed, 27 Sep 2017 07:25:56 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Wed, 27 Sep 2017 07:25:56 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Wed, 27 Sep 2017 07:25:56 -0500 Received: from ula0393675.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8RCPrQY007929; Wed, 27 Sep 2017 07:25:54 -0500 From: Keerthy To: CC: , , , , Subject: [PATCH] regulator: lp873x: Update the enable mask for LDOs and BUCKs Date: Wed, 27 Sep 2017 17:55:40 +0530 Message-ID: <1506515140-26058-1-git-send-email-j-keerthy@ti.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The reset value of the EN_PIN_CTRL bit fields of LDOs and BUCKs need not be set correctly. Hence update the enable mask to include the EN_PIN_CTRL bit. While enabling this should be set to 1 so that all the regulators are tied to EN pin. Signed-off-by: Keerthy --- drivers/regulator/lp873x-regulator.c | 19 ++++++++++--------- include/linux/mfd/lp873x.h | 4 ++++ 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/regulator/lp873x-regulator.c b/drivers/regulator/lp873x-regulator.c index 70e3df6..77bea82 100644 --- a/drivers/regulator/lp873x-regulator.c +++ b/drivers/regulator/lp873x-regulator.c @@ -20,7 +20,7 @@ #include #define LP873X_REGULATOR(_name, _id, _of, _ops, _n, _vr, _vm, _er, _em, \ - _delay, _lr, _cr) \ + _dv, _delay, _lr, _cr) \ [_id] = { \ .desc = { \ .name = _name, \ @@ -36,6 +36,7 @@ .vsel_mask = _vm, \ .enable_reg = _er, \ .enable_mask = _em, \ + .disable_val = _dv, \ .ramp_delay = _delay, \ .linear_ranges = _lr, \ .n_linear_ranges = ARRAY_SIZE(_lr), \ @@ -175,21 +176,21 @@ static int lp873x_buck_get_current_limit(struct regulator_dev *rdev) LP873X_REGULATOR("BUCK0", LP873X_BUCK_0, "buck0", lp873x_buck01_ops, 256, LP873X_REG_BUCK0_VOUT, LP873X_BUCK0_VOUT_BUCK0_VSET, LP873X_REG_BUCK0_CTRL_1, - LP873X_BUCK0_CTRL_1_BUCK0_EN, 10000, - buck0_buck1_ranges, LP873X_REG_BUCK0_CTRL_2), + LP873X_BUCK_ENABLE_MASK, LP873X_BUCK_DISABLE_VAL, + 10000, buck0_buck1_ranges, LP873X_REG_BUCK0_CTRL_2), LP873X_REGULATOR("BUCK1", LP873X_BUCK_1, "buck1", lp873x_buck01_ops, 256, LP873X_REG_BUCK1_VOUT, LP873X_BUCK1_VOUT_BUCK1_VSET, LP873X_REG_BUCK1_CTRL_1, - LP873X_BUCK1_CTRL_1_BUCK1_EN, 10000, - buck0_buck1_ranges, LP873X_REG_BUCK1_CTRL_2), + LP873X_BUCK_ENABLE_MASK, LP873X_BUCK_DISABLE_VAL, + 10000, buck0_buck1_ranges, LP873X_REG_BUCK1_CTRL_2), LP873X_REGULATOR("LDO0", LP873X_LDO_0, "ldo0", lp873x_ldo01_ops, 26, LP873X_REG_LDO0_VOUT, LP873X_LDO0_VOUT_LDO0_VSET, - LP873X_REG_LDO0_CTRL, - LP873X_LDO0_CTRL_LDO0_EN, 0, ldo0_ldo1_ranges, 0xFF), + LP873X_REG_LDO0_CTRL, LP873X_LDO_ENABLE_MASK, + LP873X_LDO_DISABLE_VAL, 0, ldo0_ldo1_ranges, 0xFF), LP873X_REGULATOR("LDO1", LP873X_LDO_1, "ldo1", lp873x_ldo01_ops, 26, LP873X_REG_LDO1_VOUT, LP873X_LDO1_VOUT_LDO1_VSET, - LP873X_REG_LDO1_CTRL, - LP873X_LDO1_CTRL_LDO1_EN, 0, ldo0_ldo1_ranges, 0xFF), + LP873X_REG_LDO1_CTRL, LP873X_LDO_ENABLE_MASK, + LP873X_LDO_DISABLE_VAL, 0, ldo0_ldo1_ranges, 0xFF), }; static int lp873x_regulator_probe(struct platform_device *pdev) diff --git a/include/linux/mfd/lp873x.h b/include/linux/mfd/lp873x.h index edbec83..53888d4 100644 --- a/include/linux/mfd/lp873x.h +++ b/include/linux/mfd/lp873x.h @@ -77,6 +77,8 @@ #define LP873X_BUCK0_CTRL_1_BUCK0_RDIS_EN BIT(2) #define LP873X_BUCK0_CTRL_1_BUCK0_EN_PIN_CTRL BIT(1) #define LP873X_BUCK0_CTRL_1_BUCK0_EN BIT(0) +#define LP873X_BUCK_ENABLE_MASK (BIT(0) | BIT(1)) +#define LP873X_BUCK_DISABLE_VAL BIT(1) #define LP873X_BUCK0_CTRL_2_BUCK0_ILIM 0x38 #define LP873X_BUCK0_CTRL_2_BUCK0_SLEW_RATE 0x07 @@ -96,6 +98,8 @@ #define LP873X_LDO0_CTRL_LDO0_RDIS_EN BIT(2) #define LP873X_LDO0_CTRL_LDO0_EN_PIN_CTRL BIT(1) #define LP873X_LDO0_CTRL_LDO0_EN BIT(0) +#define LP873X_LDO_ENABLE_MASK (BIT(0) | BIT(1)) +#define LP873X_LDO_DISABLE_VAL BIT(1) #define LP873X_LDO1_CTRL_LDO1_RDIS_EN BIT(2) #define LP873X_LDO1_CTRL_LDO1_EN_PIN_CTRL BIT(1)