From patchwork Thu Oct 19 12:43:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Faiz Abbas X-Patchwork-Id: 10016631 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 571FB602C8 for ; Thu, 19 Oct 2017 12:43:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 47EB52875F for ; Thu, 19 Oct 2017 12:43:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3CB2528D38; Thu, 19 Oct 2017 12:43:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B93032875F for ; Thu, 19 Oct 2017 12:43:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752778AbdJSMnS (ORCPT ); Thu, 19 Oct 2017 08:43:18 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:10881 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752702AbdJSMnR (ORCPT ); Thu, 19 Oct 2017 08:43:17 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v9JChGTM016259; Thu, 19 Oct 2017 07:43:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1508416996; bh=g9za46lGXsYfEBl8rje7kQAuJ1tvrhWByrPt5mZrn/Y=; h=From:To:CC:Subject:Date; b=ZXqfwujqDKyeGuHR671HC6tP5H5b8CB203+BYMTfzEZj8fN2SVV+OjM8Jd2L4wMdI ofvVFZ+8SGIHLTwxsGfLFmQCIHGgMe6z6UAF4jsg/TaXfHth/0TDmRcCw7LFc9CTqQ 33PXI3kuKfc7DwT/6uqCDiOqboDlQVMEE5X+tbak= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9JChG5h009397; Thu, 19 Oct 2017 07:43:16 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 19 Oct 2017 07:43:15 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 19 Oct 2017 07:43:15 -0500 Received: from a0230074-OptiPlex-7010.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9JChDhb023743; Thu, 19 Oct 2017 07:43:14 -0500 From: Faiz Abbas To: CC: , , , , Subject: [PATCH v2] dwc: dra7xx: Print link state to console for debug Date: Thu, 19 Oct 2017 18:13:29 +0530 Message-ID: <1508417009-30869-1-git-send-email-faiz_abbas@ti.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Enable support for printing the LTSSM link state for debugging PCI when link is down. Signed-off-by: Faiz Abbas Acked-by: Kishon Vijay Abraham I --- v2: 1. Changed dev_err() to dev_dbg() 2. Changed static char array to static const char * const 3. format changes drivers/pci/dwc/pci-dra7xx.c | 48 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index 34427a6..0e70e77 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -98,6 +98,45 @@ struct dra7xx_pcie_of_data { #define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev) +static const char * const state[] = { + "DETECT_QUIET", + "DETECT_ACT", + "POLL_ACTIVE", + "POLL_COMPLIANCE", + "POLL_CONFIG", + "PRE_DETECT_QUIET", + "DETECT_WAIT", + "CFG_LINKWD_START", + "CFG_LINKWD_ACEPT", + "CFG_LANENUM_WAIT", + "CFG_LANENUM_ACEPT", + "CFG_COMPLETE", + "CFG_IDLE", + "RCVRY_LOCK", + "RCVRY_SPEED", + "RCVRY_RCVRCFG", + "RCVRY_IDLE", + "L0", + "L0S", + "L123_SEND_EIDLE", + "L1_IDLE", + "L2_IDLE", + "L2_WAKE", + "DISABLED_ENTRY", + "DISABLED_IDLE", + "DISABLED", + "LPBK_ENTRY", + "LPBK_ACTIVE", + "LPBK_EXIT", + "LPBK_EXIT_TIMEOUT", + "HOT_RESET_ENTRY", + "HOT_RESET", + "RCVRY_EQ0", + "RCVRY_EQ1", + "RCVRY_EQ2", + "RCVRY_EQ3" +}; + static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset) { return readl(pcie->base + offset); @@ -118,6 +157,15 @@ static int dra7xx_pcie_link_up(struct dw_pcie *pci) { struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS); + u32 cmd_reg; + u32 ltssm_state; + + if (!(reg & LINK_UP)) { + cmd_reg = dra7xx_pcie_readl(dra7xx, + PCIECTRL_DRA7XX_CONF_DEVICE_CMD); + ltssm_state = (cmd_reg & GENMASK(7, 2)) >> 2; + dev_dbg(pci->dev, "Link state:%s\n", state[ltssm_state]); + } return !!(reg & LINK_UP); }