From patchwork Wed May 16 05:40:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "J, KEERTHY" X-Patchwork-Id: 10402589 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1C38E601F9 for ; Wed, 16 May 2018 05:41:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0C3C128681 for ; Wed, 16 May 2018 05:41:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 00BA6286A3; Wed, 16 May 2018 05:41:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 055C128761 for ; Wed, 16 May 2018 05:41:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751914AbeEPFlG (ORCPT ); Wed, 16 May 2018 01:41:06 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:39009 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751844AbeEPFlE (ORCPT ); Wed, 16 May 2018 01:41:04 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id w4G5eo7u031974; Wed, 16 May 2018 00:40:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1526449250; bh=0nDwU3maDQrr8NLN6juTycJA9M719hSV+k0GtVVQkLc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=RHwZRO5dSmMytuxanyHjST6EWTBACzW3tEGMq7G7G87PUa3X7fibgygSIELOqXoMX WZCU2WOUlV8bZq1FBLFJLbH7UFK+w6nwkJwb03oVx7uS5tn41y1sVM/QnizbQh0F5f l3JzA9LcqqCM65auPNCAALFnks+J6O+VcsnS46iQ= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w4G5eoMd022997; Wed, 16 May 2018 00:40:50 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Wed, 16 May 2018 00:40:49 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Wed, 16 May 2018 00:40:49 -0500 Received: from ula0393675.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w4G5egd8008219; Wed, 16 May 2018 00:40:48 -0500 From: Keerthy To: CC: , , , , , Subject: [PATCH 2/2] pinctrl: pinctrl-single: Add functions to save and restore pinctrl context Date: Wed, 16 May 2018 11:10:30 +0530 Message-ID: <1526449230-27618-3-git-send-email-j-keerthy@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1526449230-27618-1-git-send-email-j-keerthy@ti.com> References: <1526449230-27618-1-git-send-email-j-keerthy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This adds a pair of context save/restore functions to save/restore the state of a set of pinctrl registers. This simplifies some of the AM33XX PM code as some of the pinctrl registers are lost when the per power domain loses power. The pincrtl code can perform the necessary save/restore. This will also be necessary for hibernation and RTC only sleep, as all pinctrl registers all lost. Signed-off-by: Keerthy --- drivers/pinctrl/pinctrl-single.c | 95 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 94 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index a7c5eb3..3062ebb 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -16,6 +16,7 @@ #include #include #include +#include #include @@ -144,6 +145,7 @@ struct pcs_soc_data { * struct pcs_device - pinctrl device instance * @res: resources * @base: virtual address of the controller + * @saved_vals: saved values for the controller * @size: size of the ioremapped area * @dev: device entry * @np: device tree node @@ -172,11 +174,13 @@ struct pcs_soc_data { struct pcs_device { struct resource *res; void __iomem *base; + void *saved_vals; unsigned size; struct device *dev; struct device_node *np; struct pinctrl_dev *pctl; unsigned flags; +#define PCS_CONTEXT_LOSS_OFF (1 << 3) #define PCS_QUIRK_SHARED_IRQ (1 << 2) #define PCS_FEAT_IRQ (1 << 1) #define PCS_FEAT_PINCONF (1 << 0) @@ -195,6 +199,7 @@ struct pcs_device { struct list_head gpiofuncs; struct list_head irqs; struct irq_chip chip; + struct notifier_block nb; struct irq_domain *domain; struct pinctrl_desc desc; unsigned (*read)(void __iomem *reg); @@ -1649,6 +1654,86 @@ static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs, return error; } +static int pcs_save_context(struct pcs_device *pcs) +{ + int i, mux_bytes; + u64 *regsl; + u32 *regsw; + u16 *regshw; + + mux_bytes = pcs->width / BITS_PER_BYTE; + + if (!pcs->saved_vals) + pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC); + + switch (pcs->width) { + case 64: + regsl = (u64 *)pcs->saved_vals; + for (i = 0; i < pcs->size / mux_bytes; i++) + regsl[i] = pcs->read(pcs->base + i * mux_bytes); + break; + case 32: + regsw = (u32 *)pcs->saved_vals; + for (i = 0; i < pcs->size / mux_bytes; i++) + regsw[i] = pcs->read(pcs->base + i * mux_bytes); + break; + case 16: + regshw = (u16 *)pcs->saved_vals; + for (i = 0; i < pcs->size / mux_bytes; i++) + regshw[i] = pcs->read(pcs->base + i * mux_bytes); + break; + } + + return 0; +} + +static void pcs_restore_context(struct pcs_device *pcs) +{ + int i, mux_bytes; + u64 *regsl; + u32 *regsw; + u16 *regshw; + + mux_bytes = pcs->width / BITS_PER_BYTE; + + switch (pcs->width) { + case 64: + regsl = (u64 *)pcs->saved_vals; + for (i = 0; i < pcs->size / mux_bytes; i++) + pcs->write(regsl[i], pcs->base + i * mux_bytes); + break; + case 32: + regsw = (u32 *)pcs->saved_vals; + for (i = 0; i < pcs->size / mux_bytes; i++) + pcs->write(regsw[i], pcs->base + i * mux_bytes); + break; + case 16: + regshw = (u16 *)pcs->saved_vals; + for (i = 0; i < pcs->size / mux_bytes; i++) + pcs->write(regshw[i], pcs->base + i * mux_bytes); + break; + } +} + +static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v) +{ + struct pcs_device *pcs = container_of(nb, struct pcs_device, nb); + struct pcs_pdata *pdata = dev_get_platdata(pcs->dev); + + switch (cmd) { + case CPU_CLUSTER_PM_ENTER: + if (pdata->context_may_be_lost()) + pcs_save_context(pcs); + break; + case CPU_CLUSTER_PM_EXIT: + if (pdata->context_may_be_lost()) + pcs_restore_context(pcs); + break; + } + + return NOTIFY_OK; +} + static int pcs_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -1792,6 +1877,11 @@ static int pcs_probe(struct platform_device *pdev) dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size); + if (soc->flags & PCS_CONTEXT_LOSS_OFF) { + pcs->nb.notifier_call = cpu_notifier; + cpu_pm_register_notifier(&pcs->nb); + } + return pinctrl_enable(pcs->pctl); free: @@ -1807,6 +1897,9 @@ static int pcs_remove(struct platform_device *pdev) if (!pcs) return 0; + if (pcs->flags & PCS_CONTEXT_LOSS_OFF) + cpu_pm_unregister_notifier(&pcs->nb); + pcs_free_resources(pcs); return 0; @@ -1824,7 +1917,7 @@ static int pcs_remove(struct platform_device *pdev) }; static const struct pcs_soc_data pinctrl_single_am437x = { - .flags = PCS_QUIRK_SHARED_IRQ, + .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF, .irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */ .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */ };