From patchwork Thu Apr 1 05:39:03 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Balbi X-Patchwork-Id: 90068 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o315djw0005594 for ; Thu, 1 Apr 2010 05:39:45 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753048Ab0DAFjp (ORCPT ); Thu, 1 Apr 2010 01:39:45 -0400 Received: from smtp.nokia.com ([192.100.105.134]:57246 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753041Ab0DAFjo (ORCPT ); Thu, 1 Apr 2010 01:39:44 -0400 Received: from vaebh105.NOE.Nokia.com (vaebh105.europe.nokia.com [10.160.244.31]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o315dHUj024891; Thu, 1 Apr 2010 00:39:36 -0500 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by vaebh105.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 1 Apr 2010 08:39:31 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 1 Apr 2010 08:39:31 +0300 Received: from nokia.com (esdhcp04088.research.nokia.com [172.21.40.88]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o315dSdD006488 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES128-SHA bits=128 verify=NO); Thu, 1 Apr 2010 08:39:29 +0300 Date: Thu, 1 Apr 2010 08:39:03 +0300 From: Felipe Balbi To: "Balbi Felipe (Nokia-D/Helsinki)" Cc: ext Mark Brown , David Brownell , Tony Lindgren , Linux OMAP Mailing List Subject: Re: [RFC/PATCHv2 2/4] arm: omap: gpio: implement set_debounce method Message-ID: <20100401053903.GB16297@nokia.com> Reply-To: felipe.balbi@nokia.com References: <1270038435-28106-1-git-send-email-felipe.balbi@nokia.com> <1270049712-28272-3-git-send-email-felipe.balbi@nokia.com> <20100331162158.GB32025@rakim.wolfsonmicro.main> <20100331162909.GA23490@nokia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20100331162909.GA23490@nokia.com> User-Agent: Mutt/1.5.20 (2009-06-14) X-OriginalArrivalTime: 01 Apr 2010 05:39:31.0596 (UTC) FILETIME=[B4065CC0:01CAD15D] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Thu, 01 Apr 2010 05:39:46 +0000 (UTC) From 23b09f437d8bacebab676deaf52631b7eb0e8f15 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Wed, 31 Mar 2010 15:17:29 +0300 Subject: [PATCHv3] arm: omap: gpio: implement set_debounce method OMAP support debouncing of gpio lines, implement the method using gpiolib. Signed-off-by: Felipe Balbi --- Changes since v2: - enable/disable debounce clock only once arch/arm/plat-omap/gpio.c | 75 +++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 75 insertions(+), 0 deletions(-) diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 76a347b..163d88b 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -194,6 +194,7 @@ struct gpio_bank { spinlock_t lock; struct gpio_chip chip; struct clk *dbck; + unsigned dbck_enabled:1; u32 mod_usage; }; @@ -612,6 +613,65 @@ do { \ __raw_writel(l, base + reg); \ } while(0) +/** + * _set_gpio_debounce - low level gpio debounce time + * @bank: the gpio bank we're acting upon + * @gpio: the gpio number on this @gpio + * @debounce: debounce time to use + * + * OMAP's debounce time is in 31us steps so we need + * to convert and round up to the closest unit. + */ +static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, + unsigned debounce) +{ + void __iomem *reg = bank->base; + u32 val; + u32 l; + + if (debounce < 32) + debounce = 0x01; + else if (debounce > 7936) + debounce = 0xff; + else + debounce = (debounce / 0x1f) - 1; + + l = 1 << get_gpio_index(gpio); + + if (cpu_is_omap44xx()) + reg += OMAP4_GPIO_DEBOUNCINGTIME; + else + reg += OMAP24XX_GPIO_DEBOUNCE_VAL; + + __raw_writel(debounce, reg); + + reg = bank->base; + if (cpu_is_omap44xx()) + reg += OMAP4_GPIO_DEBOUNCENABLE; + else + reg += OMAP24XX_GPIO_DEBOUNCE_EN; + + val = __raw_readl(reg); + + if (debounce) { + val |= l; + if (!bank->dbck_enabled && + (cpu_is_omap34xx() || cpu_is_omap44xx())) { + clk_enable(bank->dbck); + bank->dbck_enabled = true; + } + } else { + val &= ~l; + if (bank->dbck_enabled && + (cpu_is_omap34xx() || cpu_is_omap44xx())) { + clk_disable(bank->dbck); + bank->dbck_enabled = false; + } + } + + __raw_writel(val, reg); +} + void omap_set_gpio_debounce(int gpio, int enable) { struct gpio_bank *bank; @@ -1608,6 +1668,20 @@ static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) return 0; } +static int gpio_debounce(struct gpio_chip *chip, unsigned offset, + unsigned debounce) +{ + struct gpio_bank *bank; + unsigned long flags; + + bank = container_of(chip, struct gpio_bank, chip); + spin_lock_irqsave(&bank->lock, flags); + _set_gpio_debounce(bank, offset, debounce); + spin_unlock_irqrestore(&bank->lock, flags); + + return 0; +} + static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) { struct gpio_bank *bank; @@ -1860,6 +1934,7 @@ static int __init _omap_gpio_init(void) bank->chip.direction_input = gpio_input; bank->chip.get = gpio_get; bank->chip.direction_output = gpio_output; + bank->chip.set_debounce = gpio_debounce; bank->chip.set = gpio_set; bank->chip.to_irq = gpio_2irq; if (bank_is_mpuio(bank)) { -- 1.7.0.rc0.33.g7c3932