From patchwork Tue Dec 14 06:34:50 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Walmsley X-Patchwork-Id: 408861 X-Patchwork-Delegate: paul@pwsan.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oBE6ZZ8P009753 for ; Tue, 14 Dec 2010 06:35:35 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753960Ab0LNGfd (ORCPT ); Tue, 14 Dec 2010 01:35:33 -0500 Received: from utopia.booyaka.com ([72.9.107.138]:50283 "EHLO utopia.booyaka.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751458Ab0LNGf1 (ORCPT ); Tue, 14 Dec 2010 01:35:27 -0500 Received: (qmail 13952 invoked by uid 1019); 14 Dec 2010 06:35:26 -0000 MBOX-Line: From nobody Mon Dec 13 23:34:50 2010 Subject: [PATCH 07/12] OMAP4: clock data: Export control to enable/disable CORE/PER M3 clocks To: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org From: Paul Walmsley Cc: Rajendra Nayak , Benoit Cousson Date: Mon, 13 Dec 2010 23:34:50 -0700 Message-ID: <20101214063449.21555.29647.stgit@twilight.localdomain> In-Reply-To: <20101214063308.21555.76050.stgit@twilight.localdomain> References: <20101214063308.21555.76050.stgit@twilight.localdomain> User-Agent: StGit/0.15 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Tue, 14 Dec 2010 06:35:35 +0000 (UTC) diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 80a1898..4c77613 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -610,7 +610,9 @@ static struct clk dpll_core_m3x2_ck = { .clksel = dpll_core_m6x2_div, .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, - .ops = &clkops_null, + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, + .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate, @@ -869,7 +871,9 @@ static struct clk dpll_per_m3x2_ck = { .clksel = dpll_per_m2x2_div, .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER, .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, - .ops = &clkops_null, + .ops = &clkops_omap2_dflt, + .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER, + .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, .recalc = &omap2_clksel_recalc, .round_rate = &omap2_clksel_round_rate, .set_rate = &omap2_clksel_set_rate,