From patchwork Tue Oct 4 13:37:29 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mugunthan V N X-Patchwork-Id: 9361883 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 92390600C8 for ; Tue, 4 Oct 2016 13:38:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 848E8284C5 for ; Tue, 4 Oct 2016 13:38:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 79638286B1; Tue, 4 Oct 2016 13:38:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A2AC5284C5 for ; Tue, 4 Oct 2016 13:38:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752553AbcJDNhx (ORCPT ); Tue, 4 Oct 2016 09:37:53 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:36431 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750908AbcJDNhw (ORCPT ); Tue, 4 Oct 2016 09:37:52 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id u94Dbo7V015953; Tue, 4 Oct 2016 08:37:50 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id u94DbnUG020280; Tue, 4 Oct 2016 08:37:49 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Tue, 4 Oct 2016 08:37:48 -0500 Received: from a0131834lt.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u94Dbkb4008511; Tue, 4 Oct 2016 08:37:47 -0500 From: Mugunthan V N To: CC: Grygorii Strashko , , Sekhar Nori , "David S . Miller" , Mugunthan V N Subject: [net-next PATCH] drivers: net: cpsw-phy-sel: add support to configure rgmii internal delay Date: Tue, 4 Oct 2016 19:07:29 +0530 Message-ID: <20161004133729.12564-1-mugunthanvnm@ti.com> X-Mailer: git-send-email 2.10.0.372.g6fe1b14 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support to enable CPSW RGMII internal delay (id mode) bits when rgmii internal delay is configured in phy. Signed-off-by: Mugunthan V N --- drivers/net/ethernet/ti/cpsw-phy-sel.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/net/ethernet/ti/cpsw-phy-sel.c b/drivers/net/ethernet/ti/cpsw-phy-sel.c index c3e85ac..054a8dd 100644 --- a/drivers/net/ethernet/ti/cpsw-phy-sel.c +++ b/drivers/net/ethernet/ti/cpsw-phy-sel.c @@ -30,6 +30,8 @@ #define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7) #define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6) +#define AM33XX_GMII_SEL_RGMII2_IDMODE BIT(5) +#define AM33XX_GMII_SEL_RGMII1_IDMODE BIT(4) #define GMII_SEL_MODE_MASK 0x3 @@ -48,6 +50,7 @@ static void cpsw_gmii_sel_am3352(struct cpsw_phy_sel_priv *priv, u32 reg; u32 mask; u32 mode = 0; + bool rgmii_id = false; reg = readl(priv->gmii_sel); @@ -57,10 +60,14 @@ static void cpsw_gmii_sel_am3352(struct cpsw_phy_sel_priv *priv, break; case PHY_INTERFACE_MODE_RGMII: + mode = AM33XX_GMII_SEL_MODE_RGMII; + break; + case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_TXID: mode = AM33XX_GMII_SEL_MODE_RGMII; + rgmii_id = true; break; default: @@ -83,6 +90,13 @@ static void cpsw_gmii_sel_am3352(struct cpsw_phy_sel_priv *priv, mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN; } + if (rgmii_id) { + if (slave == 0) + mode |= AM33XX_GMII_SEL_RGMII1_IDMODE; + else + mode |= AM33XX_GMII_SEL_RGMII2_IDMODE; + } + reg &= ~mask; reg |= mode;