From patchwork Wed Mar 29 01:57:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Gerlach X-Patchwork-Id: 9650789 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 38907601E9 for ; Wed, 29 Mar 2017 01:59:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 28F6B283B9 for ; Wed, 29 Mar 2017 01:59:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1DA7128447; Wed, 29 Mar 2017 01:59:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 89EEA283B9 for ; Wed, 29 Mar 2017 01:59:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751515AbdC2B7Y (ORCPT ); Tue, 28 Mar 2017 21:59:24 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:15187 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751959AbdC2B7W (ORCPT ); Tue, 28 Mar 2017 21:59:22 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v2T1wOPB016449; Tue, 28 Mar 2017 20:58:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1490752704; bh=JrRrA3Fd7UI0FaeRTcufOvUCnFaRZCzGdybzd4uTd8o=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=wUZ9ReHnvMfTRRNJQeK5mRVR8gs0ZNe7sODuF8nlNU28HzPGfgXDZ5Zr5LN4dFTdF CPTBtumOX2WUZ5D9ArDLtwFTDhc+aR3lvOYu6Po1xOWl7SSorRJwDDP8RI/qUJvM14 ptFzIYXvNs4nbq75bmXJ96jVlSEg1diB3E0JmHzs= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2T1wOoU029917; Tue, 28 Mar 2017 20:58:24 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Tue, 28 Mar 2017 20:58:24 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2T1wOkE011327; Tue, 28 Mar 2017 20:58:24 -0500 Received: from localhost (uda0274052.am.dhcp.ti.com [128.247.83.19]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v2T1wN315416; Tue, 28 Mar 2017 20:58:23 -0500 (CDT) From: Dave Gerlach To: Tony Lindgren , Santosh Shilimkar , Russell King CC: , , , Dave Gerlach , Keerthy J Subject: [PATCH 2/8] ARM: OMAP2+: timer: Add suspend-resume callbacks for clkevent device Date: Tue, 28 Mar 2017 20:57:55 -0500 Message-ID: <20170329015801.22240-3-d-gerlach@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170329015801.22240-1-d-gerlach@ti.com> References: <20170329015801.22240-1-d-gerlach@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP OMAP timer code registers two timers - one as clocksource and one as clockevent. Since AM33XX has only one usable timer in the WKUP domain one of the timers needs suspend-resume support to restore the configuration to pre-suspend state. commit adc78e6b9946 ("timekeeping: Add suspend and resume of clock event devices") introduced .suspend and .resume callbacks for clock event devices. Leverage these callbacks to have AM33XX clockevent timer behave properly across system suspend. Extend the use of the .suspend and .resume callbacks used by am335x clockevent to am437x as well. Signed-off-by: Dave Gerlach --- arch/arm/mach-omap2/timer.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 07dd692c4737..70670dfd7135 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -68,6 +68,9 @@ static struct omap_dm_timer clkev; static struct clock_event_device clockevent_gpt; +/* Clockevent hwmod for am335x and am437x suspend */ +static struct omap_hwmod *clockevent_gpt_hwmod; + #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER static unsigned long arch_timer_freq; @@ -125,6 +128,23 @@ static int omap2_gp_timer_set_periodic(struct clock_event_device *evt) return 0; } +static void omap_clkevt_idle(struct clock_event_device *unused) +{ + if (!clockevent_gpt_hwmod) + return; + + omap_hwmod_idle(clockevent_gpt_hwmod); +} + +static void omap_clkevt_unidle(struct clock_event_device *unused) +{ + if (!clockevent_gpt_hwmod) + return; + + omap_hwmod_enable(clockevent_gpt_hwmod); + __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); +} + static struct clock_event_device clockevent_gpt = { .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, @@ -358,6 +378,14 @@ static void __init omap2_gp_clockevent_init(int gptimer_id, 3, /* Timer internal resynch latency */ 0xffffffff); + if (soc_is_am33xx() || soc_is_am43xx()) { + clockevent_gpt.suspend = omap_clkevt_idle; + clockevent_gpt.resume = omap_clkevt_unidle; + + clockevent_gpt_hwmod = + omap_hwmod_lookup(clockevent_gpt.name); + } + pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name, clkev.rate); }