From patchwork Wed May 24 08:43:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Ujfalusi X-Patchwork-Id: 9745477 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0D38B6034C for ; Wed, 24 May 2017 08:45:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F29F12891A for ; Wed, 24 May 2017 08:45:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E268528929; Wed, 24 May 2017 08:45:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7917228929 for ; Wed, 24 May 2017 08:45:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S939082AbdEXIo6 (ORCPT ); Wed, 24 May 2017 04:44:58 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:20909 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S937951AbdEXIoz (ORCPT ); Wed, 24 May 2017 04:44:55 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v4O8hV71010043; Wed, 24 May 2017 03:43:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1495615411; bh=l4LDEs+DtZMWyIr++o3XNTJsyoMyx5Jh+qTd8WejZdE=; h=From:To:CC:Subject:Date; b=YKDnHz+SAqawM8qkXu0VqXSsthkwpQjUxxN8aqq/P9bsekPJMktrSYJBQZvgU2ZOP loKGsQPn3JpHklYs1OXS472bBmXx8jFD859ABDAT46x5eXFnwTKLoFufnLeMpXX9NS ZOtGno03NYv9a/Qe8DOIbWdvb5RAPayYX2ZqkWgI= Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4O8hQ3n014439; Wed, 24 May 2017 03:43:26 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.294.0; Wed, 24 May 2017 03:43:26 -0500 Received: from feketebors.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4O8hNWC003687; Wed, 24 May 2017 03:43:24 -0500 From: Peter Ujfalusi To: , , CC: , , , Subject: [PATCH] ARM: dts: am43xx-clocks: Add support for CLKOUT2 Date: Wed, 24 May 2017 11:43:41 +0300 Message-ID: <20170524084341.16698-1-peter.ujfalusi@ti.com> X-Mailer: git-send-email 2.13.0 MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the needed clock nodes for the CLKOUT2 to be usable by boards. Signed-off-by: Peter Ujfalusi Acked-by: Tero Kristo --- arch/arm/boot/dts/am43xx-clocks.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index d1d73b725f47..430be5829f8f 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -833,4 +833,40 @@ ti,bit-shift = <23>; reg = <0x4100>; }; + + clkout2_src_mux_ck: clkout2_src_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>, + <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>, + <&dpll_mpu_m2_ck>, <&dpll_extdev_ck>; + reg = <0x4108>; + }; + + clkout2_pre_div_ck: clkout2_pre_div_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&clkout2_src_mux_ck>; + ti,bit-shift = <4>; + ti,max-div = <8>; + reg = <0x4108>; + }; + + clkout2_post_div_ck: clkout2_post_div_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&clkout2_pre_div_ck>; + ti,bit-shift = <8>; + ti,max-div = <32>; + ti,index-power-of-two; + reg = <0x4108>; + }; + + clkout2_ck: clkout2_ck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkout2_post_div_ck>; + ti,bit-shift = <16>; + reg = <0x4108>; + }; };